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authorSchuyler Eldridge2017-12-19 22:13:20 -0500
committerJack Koenig2017-12-19 19:13:20 -0800
commit51e7ea067ec2d64ce57b55446263a8e40c87996c (patch)
treef68b46050ab3bb024ddbe78c67ae10df42494b58 /src/test
parente65ae599ad0384a8d9164e3637600beecb9f7b63 (diff)
Make toNamed invert serialize (#709)
Fixes #708
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/AnnotationTests.scala8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index c8a90729..7b7e7839 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -158,7 +158,7 @@ class AnnotationTests extends AnnotationSpec with Matchers {
| module Top :
| input clk: Clock
| input in: UInt<3>
- | mem m:
+ | mem m:
| data-type => {a: UInt<4>, b: UInt<4>[2]}
| depth => 8
| write-latency => 1
@@ -496,4 +496,10 @@ class AnnotationTests extends AnnotationSpec with Matchers {
resultAnno should not contain (anno("y", mod = "Child_1"))
resultAnno should not contain (manno("Child_1"))
}
+
+ "AnnotationUtils.toNamed" should "invert Named.serialize" in {
+ val x = ComponentName("component", ModuleName("module", CircuitName("circuit")))
+ val y = AnnotationUtils.toNamed(x.serialize)
+ require(x == y)
+ }
}