diff options
| author | Jack Koenig | 2017-06-27 17:25:57 -0700 |
|---|---|---|
| committer | Jack Koenig | 2017-06-27 18:50:15 -0700 |
| commit | 6f55a30b201716b6a0e72b65f6e5777b6b5d4b81 (patch) | |
| tree | 61f5f7f7f278afbcd4fe1f5d6f7c4b4e536ce117 /src/test | |
| parent | f8572ba6532359e8a0f1bc34f3eb8241a29129ab (diff) | |
Emitting reg update mux tree, only walk netlist for wires and nodes
Fixes bug where the Verilog emitter could pull the next value for a
register that feeds a second register, removing the first register from
the second register's update.
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/IntegrationSpec.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala index 6ac45b6d..647aa91b 100644 --- a/src/test/scala/firrtlTests/IntegrationSpec.scala +++ b/src/test/scala/firrtlTests/IntegrationSpec.scala @@ -11,6 +11,7 @@ import java.io.File class GCDExecutionTest extends ExecutionTest("GCDTester", "/integration") class RightShiftExecutionTest extends ExecutionTest("RightShiftTester", "/integration") class MemExecutionTest extends ExecutionTest("MemTester", "/integration") +class PipeExecutionTest extends ExecutionTest("PipeTester", "/integration") // This is a bit custom some kind of one off class GCDSplitEmissionExecutionTest extends FirrtlFlatSpec { |