diff options
| author | Adam Izraelevitz | 2017-08-23 20:12:25 -0700 |
|---|---|---|
| committer | GitHub | 2017-08-23 20:12:25 -0700 |
| commit | f3c0e9e4b268c69d49ef8c18e41c7f75398bb8cf (patch) | |
| tree | a4cb1d1bcab082dfa7610e38fe087c17055ed03b /src/test | |
| parent | 672162b4bf6ca4a4a4ed7a4a9ffaadfea428ede0 (diff) | |
Reorder port and wire assignments in Verilog (#641)
* Reorder port and wire assignments in Verilog
* Fixed up syntax
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/UnitTests.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index f717fc18..c5179819 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -127,7 +127,8 @@ class UnitTests extends FirrtlFlatSpec { "Emitting a nested expression" should "throw an exception" in { val passes = Seq( ToWorkingIR, - InferTypes) + InferTypes, + ResolveKinds) intercept[PassException] { val c = Parser.parse(splitExpTestCode.split("\n").toIterator) val c2 = passes.foldLeft(c)((c, p) => p run c) |