From f3c0e9e4b268c69d49ef8c18e41c7f75398bb8cf Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Wed, 23 Aug 2017 20:12:25 -0700
Subject: Reorder port and wire assignments in Verilog (#641)

* Reorder port and wire assignments in Verilog

* Fixed up syntax
---
 src/test/scala/firrtlTests/UnitTests.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index f717fc18..c5179819 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -127,7 +127,8 @@ class UnitTests extends FirrtlFlatSpec {
   "Emitting a nested expression" should "throw an exception" in {
     val passes = Seq(
       ToWorkingIR,
-      InferTypes)
+      InferTypes,
+      ResolveKinds)
     intercept[PassException] {
       val c = Parser.parse(splitExpTestCode.split("\n").toIterator)
       val c2 = passes.foldLeft(c)((c, p) => p run c)
-- 
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