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authorJack Koenig2017-06-29 16:04:13 -0700
committerJack Koenig2017-06-29 21:16:13 -0700
commita43486b65506620f89f3e171101353b2dde65351 (patch)
treea46e85ea7ea56e80596b645f4619f6f74ae1ad56 /src/test
parentad3c3a6fcb5bc374bd56c7dd2591fb1def1a5e1b (diff)
Preserve "better" names in Constant Propagation
Names that do not start with '_' are "better" than those that do
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/ConstantPropagationTests.scala103
1 files changed, 101 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index f818f9c0..8f09ac9e 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -372,13 +372,92 @@ class ConstantPropagationSpec extends FirrtlFlatSpec {
"""
(parse(exec(input))) should be (parse(check))
}
+
+ // =============================
+ "ConstProp" should "swap named nodes with temporary nodes that drive them" in {
+ val input =
+"""circuit Top :
+ module Top :
+ input x : UInt<1>
+ input y : UInt<1>
+ output z : UInt<1>
+ node _T_1 = and(x, y)
+ node n = _T_1
+ z <= n
+"""
+ val check =
+"""circuit Top :
+ module Top :
+ input x : UInt<1>
+ input y : UInt<1>
+ output z : UInt<1>
+ node n = and(x, y)
+ node _T_1 = n
+ z <= n
+"""
+ (parse(exec(input))) should be (parse(check))
+ }
+
+ // =============================
+ "ConstProp" should "swap named nodes with temporary wires that drive them" in {
+ val input =
+"""circuit Top :
+ module Top :
+ input x : UInt<1>
+ input y : UInt<1>
+ output z : UInt<1>
+ wire _T_1 : UInt<1>
+ node n = _T_1
+ z <= n
+ _T_1 <= and(x, y)
+"""
+ val check =
+"""circuit Top :
+ module Top :
+ input x : UInt<1>
+ input y : UInt<1>
+ output z : UInt<1>
+ wire n : UInt<1>
+ node _T_1 = n
+ z <= n
+ n <= and(x, y)
+"""
+ (parse(exec(input))) should be (parse(check))
+ }
+
+ // =============================
+ "ConstProp" should "swap named nodes with temporary registers that drive them" in {
+ val input =
+"""circuit Top :
+ module Top :
+ input clock : Clock
+ input x : UInt<1>
+ output z : UInt<1>
+ reg _T_1 : UInt<1>, clock with : (reset => (UInt<1>(0), _T_1))
+ node n = _T_1
+ z <= n
+ _T_1 <= x
+"""
+ val check =
+"""circuit Top :
+ module Top :
+ input clock : Clock
+ input x : UInt<1>
+ output z : UInt<1>
+ reg n : UInt<1>, clock with : (reset => (UInt<1>(0), n))
+ node _T_1 = n
+ z <= n
+ n <= x
+"""
+ (parse(exec(input))) should be (parse(check))
+ }
}
// More sophisticated tests of the full compiler
class ConstantPropagationIntegrationSpec extends LowTransformSpec {
def transform = new LowFirrtlOptimization
- "ConstProp" should "should not optimize across dontTouch on nodes" in {
+ "ConstProp" should "NOT optimize across dontTouch on nodes" in {
val input =
"""circuit Top :
| module Top :
@@ -396,7 +475,7 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
execute(input, check, Seq(dontTouch("Top.z")))
}
- it should "should not optimize across dontTouch on wires" in {
+ it should "NOT optimize across dontTouch on wires" in {
val input =
"""circuit Top :
| module Top :
@@ -415,4 +494,24 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
| z <= x""".stripMargin
execute(input, check, Seq(dontTouch("Top.z")))
}
+
+ it should "still propagate constants even when there is name swapping" in {
+ val input =
+ """circuit Top :
+ | module Top :
+ | input x : UInt<1>
+ | input y : UInt<1>
+ | output z : UInt<1>
+ | node _T_1 = and(and(x, y), UInt<1>(0))
+ | node n = _T_1
+ | z <= n""".stripMargin
+ val check =
+ """circuit Top :
+ | module Top :
+ | input x : UInt<1>
+ | input y : UInt<1>
+ | output z : UInt<1>
+ | z <= UInt<1>(0)""".stripMargin
+ execute(input, check, Seq.empty)
+ }
}