diff options
| author | Shreesha Srinath | 2017-06-12 14:21:15 -0700 |
|---|---|---|
| committer | Jack Koenig | 2017-06-12 14:21:15 -0700 |
| commit | 50fb23572c78463d44a071d575c8f2212a048f8e (patch) | |
| tree | 97161bbe1bf270e7b223d8c1e2ed80d49dffbc9a /src/test | |
| parent | fb26097de2d4ee535783eb575ad04e6a410a5e46 (diff) | |
Fixes a typo in the verilog `elsif code generation (#603)
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/AttachSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala index 93a36f70..6e5883d7 100644 --- a/src/test/scala/firrtlTests/AttachSpec.scala +++ b/src/test/scala/firrtlTests/AttachSpec.scala @@ -129,7 +129,7 @@ class InoutVerilogSpec extends FirrtlFlatSpec { | assign a2 = x; | assign a1 = a2; | assign a2 = a1; - | `elseif verilator + | `elsif verilator | `error "Verilator does not support alias and thus cannot arbirarily connect bidirectional wires and ports" | `else | alias x = a1 = a2; @@ -147,7 +147,7 @@ class InoutVerilogSpec extends FirrtlFlatSpec { | input foo : { b : UInt<3>, a : Analog<3> } | output bar : { b : UInt<3>, a : Analog<3> } | bar <- foo""".stripMargin - // Omitting `ifdef SYNTHESIS and `elseif verilator since it's tested above + // Omitting `ifdef SYNTHESIS and `elsif verilator since it's tested above val check = """module Attaching( | input [2:0] foo_b, |