From 50fb23572c78463d44a071d575c8f2212a048f8e Mon Sep 17 00:00:00 2001
From: Shreesha Srinath
Date: Mon, 12 Jun 2017 14:21:15 -0700
Subject: Fixes a typo in the verilog `elsif code generation (#603)

---
 src/test/scala/firrtlTests/AttachSpec.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index 93a36f70..6e5883d7 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -129,7 +129,7 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |    assign a2 = x;
         |    assign a1 = a2;
         |    assign a2 = a1;
-        |  `elseif verilator
+        |  `elsif verilator
         |    `error "Verilator does not support alias and thus cannot arbirarily connect bidirectional wires and ports"
         |  `else
         |    alias x = a1 = a2;
@@ -147,7 +147,7 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
          |    input foo : { b : UInt<3>, a : Analog<3> }
          |    output bar : { b : UInt<3>, a : Analog<3> }
          |    bar <- foo""".stripMargin
-    // Omitting `ifdef SYNTHESIS and `elseif verilator since it's tested above
+    // Omitting `ifdef SYNTHESIS and `elsif verilator since it's tested above
     val check =
       """module Attaching(
         |  input  [2:0] foo_b,
-- 
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