diff options
| author | Jack Koenig | 2017-09-29 15:43:15 -0700 |
|---|---|---|
| committer | GitHub | 2017-09-29 15:43:15 -0700 |
| commit | 5e23294dc6ac3c1937c9f071f970178c9f724037 (patch) | |
| tree | b7f16f9895154ed9bed6dab389793b5731825dee /src/test | |
| parent | cd8542d31f20511844c59e08527af73d1e3f6ae1 (diff) | |
StringLit.verilogEscape should support all printable ASCII chars (#668)
Defined as the range from ' ' to '~' [0x20, 0x7e]
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/StringSpec.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala index 87ee9191..f1f0bbde 100644 --- a/src/test/scala/firrtlTests/StringSpec.scala +++ b/src/test/scala/firrtlTests/StringSpec.scala @@ -66,6 +66,9 @@ class StringSpec extends FirrtlPropSpec { val lit = StringLit.unescape(whitelist) // Check result assert(lit.serialize == whitelist) + // Scala likes to escape ' as \', Verilog doesn't + val verilogWhitelist = whitelist.replaceAll("""\\'""", "'") + assert(lit.verilogEscape.tail.init == verilogWhitelist) } // Valid escapes = \n, \t, \\, \", \' |