From 5e23294dc6ac3c1937c9f071f970178c9f724037 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Fri, 29 Sep 2017 15:43:15 -0700
Subject: StringLit.verilogEscape should support all printable ASCII chars
 (#668)

Defined as the range from ' ' to '~' [0x20, 0x7e]---
 src/test/scala/firrtlTests/StringSpec.scala | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala
index 87ee9191..f1f0bbde 100644
--- a/src/test/scala/firrtlTests/StringSpec.scala
+++ b/src/test/scala/firrtlTests/StringSpec.scala
@@ -66,6 +66,9 @@ class StringSpec extends FirrtlPropSpec {
     val lit = StringLit.unescape(whitelist)
     // Check result
     assert(lit.serialize == whitelist)
+    // Scala likes to escape ' as \', Verilog doesn't
+    val verilogWhitelist = whitelist.replaceAll("""\\'""", "'")
+    assert(lit.verilogEscape.tail.init == verilogWhitelist)
   }
 
   // Valid escapes = \n, \t, \\, \", \'
-- 
cgit v1.2.3