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Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/StringSpec.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala index 87ee9191..f1f0bbde 100644 --- a/src/test/scala/firrtlTests/StringSpec.scala +++ b/src/test/scala/firrtlTests/StringSpec.scala @@ -66,6 +66,9 @@ class StringSpec extends FirrtlPropSpec { val lit = StringLit.unescape(whitelist) // Check result assert(lit.serialize == whitelist) + // Scala likes to escape ' as \', Verilog doesn't + val verilogWhitelist = whitelist.replaceAll("""\\'""", "'") + assert(lit.verilogEscape.tail.init == verilogWhitelist) } // Valid escapes = \n, \t, \\, \", \' |