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AgeCommit message (Expand)Author
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
2020-01-15improve the tail ir usability. (#1241)Sequencer
2020-01-15Filter ResolvePaths in EliminateTargetPaths (#1310)Schuyler Eldridge
2020-01-10Change LoggerState.globalLevel to Warn (#1307)Jim Lawson
2020-01-09Dedup PassTests, add NoCircuitDedupAnnotations (#1302)Schuyler Eldridge
2020-01-07Remove printlns from testsJack Koenig
2020-01-07Switch compileFirrtlTest from Driver to FirrtlStageJack Koenig
2020-01-07Redirect testing shell commands to loggerJack Koenig
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
2019-12-30Respect last connect semantics in InferResetsJack Koenig
2019-11-29Remove scala-logging fully in favor of our own loggerJack Koenig
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
2019-11-14Add test with Transform inside objectSchuyler Eldridge
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
2019-11-04Merge branch 'master' into serialization-utilsJack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
2019-11-04Add explicit EOF to top-level parser rule (#1217)Albert Magyar
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-30Add some simple tests to demonstrate how to provide type hintsDavid Biancolin
2019-10-29Change findInstancesInHierarchy to return implicit top instanceAlbert Magyar
2019-10-22Add Register Updates/else-if Verilog Emitter testsSchuyler Eldridge
2019-10-21Add tests for memories with latency >1, toggling enablesAlbert Magyar
2019-10-21Add library for streamlined Verilog execution testsAlbert Magyar
2019-10-21Add test for #1179: comb-loops from VerilogMemDelaysAlbert Magyar
2019-10-18Upstream intervals (#870)Adam Izraelevitz
2019-10-08Add test for TopWiringTransform idempotencySchuyler Eldridge
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
2019-09-30Improve read-under-write parameter supportAlbert Magyar
2019-09-19Faster inline renaming (#1184)Albert Chen
2019-09-16Rename gender to flowSchuyler Eldridge
2019-09-12update inline transform and testcasesAbert Chen
2019-09-05clean up spacing in inline testabejgonzalez
2019-08-19Refactor exceptions to remove stack trace from user errors (#1157)Jack Koenig
2019-08-13Infer reset (#1068)Jack Koenig
2019-08-07Add tests on RemoveReset of invalid initsSchuyler Eldridge
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
2019-08-07DRY check chirrtl (#1148)Albert Magyar
2019-08-05Add FileUtilsSpecSchuyler Eldridge
2019-08-01Followup to PR #1142chick
2019-08-01Followup to PR #1142chick
2019-07-25Allow name of blackbox resource .f file to change from static value (#1129)Albert Magyar
2019-07-24Add ExpandConnects to TopWiringTransform fixup (#1135)Schuyler Eldridge
2019-07-21Fix RenameMap chaining (#1126)Albert Chen
2019-07-19Add SimplifyMems transform to lower memories without splitting (#1111)Albert Magyar
2019-07-19Fix renaming of annotations with paths (#967)Albert Chen
2019-07-15Add type aliases for dependenciesSchuyler Eldridge
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