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2016-08-15Remove stanza (#231)Adam Izraelevitz
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-02-10Re-enable some passesPalmer Dabbelt
These were accidentally removed.
2016-02-09Added license to FIRRTL filesazidar
2016-02-09More bug fixesazidar
2016-02-09Moved check-high-form to operate on working irazidar
2016-02-09WIP, nothing works. Starting creating working IR and necessary utilsazidar
2016-01-28Added addw to working ir as an optimized verilog emissionazidar
2016-01-25Added verilog rename passazidar
2016-01-25Fixed support for muxes and nodes with passive aggregate typesazidar
2016-01-23Added inference to mportsazidar
2016-01-23Changed chirrtl to not require known mask valuesazidar
2016-01-20WIP, need to update chirrtl with new mask syntaxazidar
2016-01-16Standard Verilog doesn't use Resolve(), but lists out the resolution passes ↵azidar
individually
2016-01-16Fixed up minor errors after rebase onto masterazidar
2016-01-16Commented back in Starting and Finishing for testingazidar
2016-01-16Added more data in printout of time to compileazidar
2016-01-16Sped up some passes. Added global mname to allow easy per-module hashes for ↵azidar
accellerating functions
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16WIP Almost there, need to generate enable connectionsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵azidar
roadblock in assigning clocked ports
2016-01-16Finished supporting nested accesses. Required some nuianced thinking. Pass ↵azidar
all feature tests. Deleted CondRead because it tested a problem we don't have any more
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about ↵azidar
emitting ports (and the assignments to them)
2016-01-16WIP. Compiles and there's some outputazidar
2016-01-16WIPazidar
2016-01-16Fixed inline-indexers bug where genders weren't properly calculated inazidar
Lower Types pass. #53
2015-12-11Added LoFirrtl compiler, can be called with -X lofirrtlazidar
2015-10-30Added support for -b <backend> so that specific passes can be run then a ↵jackkoenig
backend can be applied. Added firrtl compiler for emitting firrtl
2015-09-30Moved To-Real-Ir earlier, so CheckWidth could happen before PadWidthazidar
2015-09-29Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect ↵azidar
catching of initialization of accessors. Missing use case of accessing an accessor. Still need to update tests to pass
2015-08-28Moved check type and check kind after check genderazidar
2015-08-25Added width check pass with tests. #22.azidar
2015-08-19Added beginning of constant propagation pass, doesn't workazidar
2015-08-05Added type inference before gender checkazidar
2015-08-04Added check for reading from outputs with flipsazidar
2015-07-30Added module name to error messages.azidar
2015-07-21Firrtl generates verilog that compiles, but does not workAdam Izraelevitz
2015-07-21Fixed bug in fix :Pazidar
2015-07-21Fixed removing non-referenced componentsazidar
2015-07-21Made things go faster. Still in progress. Expand when now removesAdam Izraelevitz
non-referenced declarations that are not instances, but it doesn't work right now.
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
Had to separate initialization check pass Need to write dead code elimination pass Added LongWidth to support dshl that are huge
2015-07-16Fixed rename to work with chisel3 stuffazidar
2015-07-14Fixed performance bug in backend. Added renamingazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Added clock supportazidar
2015-07-14Updated flo backendazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-02Fixed stanza, optimize works, added a time printoutazidar
2015-06-03Fixed verilog backend bugs. Passes ALU. Fails Datapathazidar
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