diff options
| author | azidar | 2015-12-12 17:23:20 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | bc4b0e9d2e9ba32f7fbb9813d31df306fb7a8e0e (patch) | |
| tree | bb22fe87dedc365b4bccdb3f0e7932a7dbe567c1 /src/main/stanza/compilers.stanza | |
| parent | 28e4c6a09011cafdd1e3533118f7c3499e0d3dc6 (diff) | |
WIP Almost there, need to generate enable connections
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 5cda6325..6ede59ad 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -2,6 +2,7 @@ defpackage firrtl/compiler : import core import verse import firrtl/passes + import firrtl/chirrtl ;import firrtl/errors ;import firrtl/flo ;import firrtl/verilog @@ -48,6 +49,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ;RemoveSpecialChars() ;R ;CheckHighForm() ;R ;TempElimination() ;R ; Needs to check number of uses + ToIR() ;R -> W ToWorkingIR() ;R -> W ResolveKinds() ;W InferTypes() ;R |