From bc4b0e9d2e9ba32f7fbb9813d31df306fb7a8e0e Mon Sep 17 00:00:00 2001
From: azidar
Date: Sat, 12 Dec 2015 17:23:20 -0800
Subject: WIP Almost there, need to generate enable connections

---
 src/main/stanza/compilers.stanza | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/main/stanza/compilers.stanza')

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 5cda6325..6ede59ad 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -2,6 +2,7 @@ defpackage firrtl/compiler :
   import core
   import verse
   import firrtl/passes
+  import firrtl/chirrtl
   ;import firrtl/errors
   ;import firrtl/flo
   ;import firrtl/verilog
@@ -48,6 +49,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       ;RemoveSpecialChars()     ;R
       ;CheckHighForm()          ;R
       ;TempElimination()        ;R         ; Needs to check number of uses
+      ToIR()            ;R -> W
       ToWorkingIR()            ;R -> W
       ResolveKinds()           ;W
       InferTypes()             ;R
-- 
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