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authorAdam Izraelevitz2016-08-15 10:32:41 -0700
committerGitHub2016-08-15 10:32:41 -0700
commitbebd04c4c68c320b2b72325e348c726dc33beae6 (patch)
tree69f6d4da577977cc7ff428b0545bb4735507aad0 /src/main/stanza/compilers.stanza
parentcca37c46fc0848f5dbf5f95ba60755ed6d60712b (diff)
Remove stanza (#231)
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
Diffstat (limited to 'src/main/stanza/compilers.stanza')
-rw-r--r--src/main/stanza/compilers.stanza235
1 files changed, 0 insertions, 235 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
deleted file mode 100644
index 1054b622..00000000
--- a/src/main/stanza/compilers.stanza
+++ /dev/null
@@ -1,235 +0,0 @@
-;Copyright (c) 2014 - 2016 The Regents of the University of
-;California (Regents). All Rights Reserved. Redistribution and use in
-;source and binary forms, with or without modification, are permitted
-;provided that the following conditions are met:
-; * Redistributions of source code must retain the above
-; copyright notice, this list of conditions and the following
-; two paragraphs of disclaimer.
-; * Redistributions in binary form must reproduce the above
-; copyright notice, this list of conditions and the following
-; two paragraphs of disclaimer in the documentation and/or other materials
-; provided with the distribution.
-; * Neither the name of the Regents nor the names of its contributors
-; may be used to endorse or promote products derived from this
-; software without specific prior written permission.
-;IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT,
-;SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS,
-;ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF
-;REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT
-;LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-;A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF
-;ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION
-;TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
-;MODIFICATIONS.
-defpackage firrtl/compiler :
- import core
- import verse
- import firrtl/passes
- import firrtl/chirrtl
- import firrtl/errors
- ;import firrtl/flo
- ;import firrtl/verilog
- import firrtl/ir2
- import firrtl/ir-utils
- import firrtl/firrtl
-
-;public defstruct StandardFlo <: Compiler :
-; with-output : (() -> False) -> False with: (as-method => true)
-;public defmethod passes (c:StandardFlo) -> List<Pass> :
-; to-list $ [
-; RemoveSpecialChars()
-; RemoveScopes()
-; CheckHighForm()
-; ;; TempElimination()
-; ToWorkingIR()
-; ResolveKinds()
-; CheckKinds()
-; InferTypes()
-; CheckTypes()
-; ResolveGenders()
-; CheckGenders()
-; ExpandAccessors()
-; LowerToGround()
-; InlineIndexed()
-; ExpandWhens()
-; InferWidths()
-; Pad()
-; Inline()
-; SplitExp()
-; ToRealIR()
-; CheckWidths()
-; ;RemoveSpecialChars()
-; CheckHighForm()
-; CheckLowForm()
-; Flo(with-output(c))
-; ]
-
-public defstruct StandardVerilog <: Compiler :
- with-output : (() -> False) -> False with: (as-method => true)
-public defmethod backend (c:StandardVerilog) -> List<Pass> :
- to-list $ [ Verilog(with-output(c)) ]
-public defmethod passes (c:StandardVerilog) -> List<Pass> :
- to-list $ [
- ;RemoveSpecialChars()
- ;TempElimination() ; Needs to check number of uses
- ;===============
- CInferTypes()
- CInferMDir()
- RemoveCHIRRTL()
- ;===============
- ToWorkingIR()
- ;===============
- CheckHighForm()
- ;===============
- ResolveKinds()
- InferTypes()
- CheckTypes()
- ResolveGenders()
- CheckGenders()
- InferWidths()
- CheckWidths()
- ;===============
- PullMuxes()
- ;===============
- ExpandConnects()
- ;===============
- RemoveAccesses()
- ;===============
- ExpandWhens()
- ;===============
- CheckInitialization()
- ;===============
- ConstProp()
- ;===============
- ResolveKinds()
- InferTypes()
- CheckTypes()
- ResolveGenders()
- CheckGenders()
- InferWidths()
- CheckWidths()
- ;===============
- LowerTypes()
- ;===============
- ResolveKinds()
- InferTypes()
- CheckTypes()
- ResolveGenders()
- CheckGenders()
- InferWidths()
- CheckWidths()
- ;===============
- VerilogWrap()
- SplitExp()
- VerilogRename()
- Verilog(with-output(c))
- ;===============
- ;ToRealIR()
- ;Pad()
- ;CheckWidths()
- ;CheckHighForm()
- ;CheckLowForm()
- ;Verilog(with-output(c))
- ]
-
-public defstruct StandardFIRRTL <: Compiler :
- with-output : (() -> False) -> False with: (as-method => true)
-public defmethod backend (c:StandardFIRRTL) -> List<Pass> :
- to-list $ [ FIRRTL(with-output(c)) ]
-public defmethod passes (c:StandardFIRRTL) -> List<Pass> :
- to-list $ [
- FIRRTL(with-output(c))
- ]
-
-public defstruct StandardLoFIRRTL <: Compiler :
- with-output : (() -> False) -> False with: (as-method => true)
-public defmethod backend (c:StandardLoFIRRTL) -> List<Pass> :
- to-list $ [ FIRRTL(with-output(c)) ]
-public defmethod passes (c:StandardLoFIRRTL) -> List<Pass> :
- to-list $ [
- ;===============
- RemoveCHIRRTL()
- ;===============
- CheckHighForm()
- ;===============
- ToWorkingIR()
- ;===============
- ResolveKinds()
- InferTypes()
- CheckTypes()
- ResolveGenders()
- CheckGenders()
- InferWidths()
- CheckWidths()
- ;===============
- Resolve()
- ;===============
- ExpandConnects()
- ;===============
- RemoveAccesses()
- ;===============
- ExpandWhens()
- ;===============
- CheckInitialization()
- ;===============
- ConstProp()
- ;===============
- ResolveKinds()
- InferTypes()
- CheckTypes()
- ResolveGenders()
- CheckGenders()
- InferWidths()
- CheckWidths()
- ;===============
- LowerTypes()
- ;===============
- ResolveKinds()
- InferTypes()
- CheckTypes()
- ResolveGenders()
- CheckGenders()
- InferWidths()
- CheckWidths()
- ;===============
- SplitExp()
- ;===============
- FIRRTL(with-output(c))
- ]
-
-;============= DRIVER ======================================
-public defn run-backend (c:Circuit,pass:Pass) :
- run-passes(c,list(pass))
-public defn run-passes (c:Circuit,comp:Compiler) -> Circuit:
- run-passes(c,passes(comp))
-public defn run-passes (c:Circuit,ls:List<Pass>) -> Circuit:
- var c*:Circuit = c
- println("Compiling!")
- if PRINT-CIRCUITS : println("Original Circuit")
- if PRINT-CIRCUITS : print(c)
- ;val start-time = current-time-us()
- val start-time = to-int(to-string(current-time-us() / to-long(1000)))
- var t = start-time
- val time-table = Vector<[String,Int]>()
- for p in ls do :
- println-all(["Starting " name(p)])
- if PRINT-CIRCUITS : println(name(p))
- c* = pass(p)(c*)
- if PRINT-CIRCUITS : print(c*)
- val current-time = to-int(to-string(current-time-us() / to-long(1000)))
- println-all(["Finished " name(p)])
- println-all(["Milliseconds since start: " current-time - start-time])
- println-all(["Milliseconds for this pass: " current-time - t])
- println-all(["\n"])
- ;println-all([current-time - t])
- add(time-table,[name(p), current-time - t])
- t = current-time
-
- println("===== Time Breakdown =====")
- for x in time-table do :
- println-all([x[0] " --- " to-float(x[1] as Int * 100) / to-float(t - start-time) "%" " --- " to-float(x[1] as Int * 100) "ms"])
- println-all(["Total Time --- " to-float(t - start-time) "ms"])
- println("==========================")
- println("Done!")
- c*