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authorAdam Izraelevitz2015-07-21 17:30:43 -0700
committerAdam Izraelevitz2015-07-21 17:30:43 -0700
commit5fadf1210fb358e1f9aff628da8d369efdde9b4e (patch)
treeb7819b114ec0b42021a47cef77fc9dd2271d67d4 /src/main/stanza/compilers.stanza
parent86dfd891ee40a9ff367984ec285013cc8e5b37c3 (diff)
Firrtl generates verilog that compiles, but does not work
Diffstat (limited to 'src/main/stanza/compilers.stanza')
-rw-r--r--src/main/stanza/compilers.stanza2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 063feb6f..c087e66e 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -96,6 +96,6 @@ public defn run-passes (c:Circuit,ls:List<Pass>) :
println(STANDARD-ERROR,"===== Time Breakdown =====")
for x in time-table do :
- println-all(STANDARD-ERROR,[x[0] " --- " to-float(x[1] as Int) / to-float(t - start-time) "%"])
+ println-all(STANDARD-ERROR,[x[0] " --- " to-float(x[1] as Int * 100) / to-float(t - start-time) "%"])
println(STANDARD-ERROR,"==========================")
println("Done!")