From 5fadf1210fb358e1f9aff628da8d369efdde9b4e Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Tue, 21 Jul 2015 17:30:43 -0700
Subject: Firrtl generates verilog that compiles, but does not work

---
 src/main/stanza/compilers.stanza | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/main/stanza/compilers.stanza')

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 063feb6f..c087e66e 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -96,6 +96,6 @@ public defn run-passes (c:Circuit,ls:List<Pass>) :
 
    println(STANDARD-ERROR,"===== Time Breakdown =====")
    for x in time-table do :
-      println-all(STANDARD-ERROR,[x[0] " --- " to-float(x[1] as Int) / to-float(t - start-time) "%"])
+      println-all(STANDARD-ERROR,[x[0] " --- " to-float(x[1] as Int * 100) / to-float(t - start-time) "%"])
    println(STANDARD-ERROR,"==========================")
    println("Done!")
-- 
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