diff options
| author | azidar | 2015-08-25 14:13:00 -0700 |
|---|---|---|
| committer | azidar | 2015-08-25 14:13:13 -0700 |
| commit | eb1ab67b6cc3fd4a549da563bf643bd519d7562e (patch) | |
| tree | a21f0ca828398a33a68f38209429cc6beed86edc /src/main/stanza/compilers.stanza | |
| parent | 6cd96b6315c32bbf6c4ace28197ff1d4be86a129 (diff) | |
Added width check pass with tests. #22.
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index eb0a36c4..b9a3028a 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -32,6 +32,7 @@ public defmethod passes (c:StandardFlo) -> List<Pass> : Inline() SplitExp() ToRealIR() + CheckWidths() ;RemoveSpecialChars() CheckHighForm() CheckLowForm() @@ -42,34 +43,33 @@ public defstruct StandardVerilog <: Compiler : with-output : (() -> False) -> False with: (as-method => true) public defmethod passes (c:StandardVerilog) -> List<Pass> : to-list $ [ - RemoveSpecialChars() - RemoveScopes() - CheckHighForm() - TempElimination() - ToWorkingIR() - ;; MakeExplicitReset() - ResolveKinds() - CheckKinds() - InferTypes() - CheckTypes() - ResolveGenders() - CheckGenders() - ExpandAccessors() - LowerToGround() - ExpandIndexedConnects() - InferTypes() - CheckGenders() - ExpandWhens() - InferWidths() - ;Pad() - ConstProp() - SplitExp() - ToRealIR() - ;RemoveSpecialChars() - CheckHighForm() - CheckLowForm() - CheckInitialization() - Verilog(with-output(c)) + RemoveSpecialChars() ;R + RemoveScopes() ;R + CheckHighForm() ;R + TempElimination() ;R + ToWorkingIR() ;R -> W + ResolveKinds() ;W + CheckKinds() ;W + InferTypes() ;R + CheckTypes() ;R + ResolveGenders() ;W + CheckGenders() ;W + ExpandAccessors() ;W + LowerToGround() ;W + ExpandIndexedConnects() ;W + InferTypes() ;R + CheckGenders() ;W + ExpandWhens() ;W + InferWidths() ;R + Pad() ;R + ConstProp() ;R + SplitExp() ;R + ToRealIR() ;W -> R + CheckWidths() ;R + CheckHighForm() ;R + CheckLowForm() ;R + CheckInitialization() ;R + Verilog(with-output(c)) ;R ] |