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| author | azidar | 2015-11-06 19:04:57 -0800 |
|---|---|---|
| committer | azidar | 2016-01-16 14:28:17 -0800 |
| commit | ece8ec00868c182e141e8d1ac75bfb60bfaa87ec (patch) | |
| tree | 3e70d8caf031486e5178e43306b7c5658e1589d9 /src/main/stanza/compilers.stanza | |
| parent | 9113d54b61b681215a3cc9fcf44e64167fad0568 (diff) | |
WIP. Compiles and there's some output
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index bed150ba..9dda33fe 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -71,11 +71,12 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : ;Pad() ;R ConstProp() ;R SplitExp() ;R + LowerTypes() ;R ;CheckWidths() ;R ;CheckHighForm() ;R ;CheckLowForm() ;R ;CheckInitialization() ;R - ;Verilog(with-output(c)) ;R + Verilog(with-output(c)) ;R ] public defstruct StandardFIRRTL <: Compiler : |