From ece8ec00868c182e141e8d1ac75bfb60bfaa87ec Mon Sep 17 00:00:00 2001
From: azidar
Date: Fri, 6 Nov 2015 19:04:57 -0800
Subject: WIP. Compiles and there's some output

---
 src/main/stanza/compilers.stanza | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/main/stanza/compilers.stanza')

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index bed150ba..9dda33fe 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -71,11 +71,12 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       ;Pad()                    ;R
       ConstProp()              ;R
       SplitExp()               ;R
+      LowerTypes()               ;R
       ;CheckWidths()            ;R
       ;CheckHighForm()          ;R
       ;CheckLowForm()           ;R
       ;CheckInitialization()    ;R
-      ;Verilog(with-output(c))  ;R
+      Verilog(with-output(c))  ;R
    ]
 
 public defstruct StandardFIRRTL <: Compiler :
-- 
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