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| author | azidar | 2015-06-03 20:39:41 -0700 |
|---|---|---|
| committer | azidar | 2015-06-03 20:39:41 -0700 |
| commit | 887d785ecc2ba7c363194cef89b72bc026c81cf9 (patch) | |
| tree | 350224acd106b5e5a4bbfccef793ac412a86b556 /src/main/stanza/compilers.stanza | |
| parent | 0a0c2d7c13c5beaa7c5132963112cc9e747ff287 (diff) | |
Fixed verilog backend bugs. Passes ALU. Fails Datapath
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index f86493a2..7b5f126c 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -43,7 +43,7 @@ public defstruct StandardVerilog <: Compiler : public defmethod passes (c:StandardVerilog) -> List<Pass> : to-list $ [ CheckHighForm(expand-delin) - ;; TempElimination() + TempElimination() ToWorkingIR() MakeExplicitReset() ResolveKinds() |