diff options
| author | azidar | 2016-01-25 15:59:59 -0800 |
|---|---|---|
| committer | azidar | 2016-01-25 15:59:59 -0800 |
| commit | eeb565de1005927bcfd7bde15bd1d4e09394cb78 (patch) | |
| tree | 832225a9cb8fbdb3f9a5483a90c5eb581508e780 /src/main/stanza/compilers.stanza | |
| parent | 25131f76567f92f18a46c41156f3a88b319591de (diff) | |
Added verilog rename pass
Diffstat (limited to 'src/main/stanza/compilers.stanza')
| -rw-r--r-- | src/main/stanza/compilers.stanza | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza index 1140e635..3ca4f8da 100644 --- a/src/main/stanza/compilers.stanza +++ b/src/main/stanza/compilers.stanza @@ -98,6 +98,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> : InferWidths() CheckWidths() ;=============== + VerilogRename() Verilog(with-output(c)) ;=============== ;ToRealIR() |