From eeb565de1005927bcfd7bde15bd1d4e09394cb78 Mon Sep 17 00:00:00 2001
From: azidar
Date: Mon, 25 Jan 2016 15:59:59 -0800
Subject: Added verilog rename pass

---
 src/main/stanza/compilers.stanza | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/main/stanza/compilers.stanza')

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index 1140e635..3ca4f8da 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -98,6 +98,7 @@ public defmethod passes (c:StandardVerilog) -> List<Pass> :
       InferWidths()
       CheckWidths()
       ;===============
+      VerilogRename() 
       Verilog(with-output(c)) 
       ;===============
       ;ToRealIR()             
-- 
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