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AgeCommit message (Expand)Author
2020-07-15ir: store FileInfo string in escaped format (#1690)Kevin Laeufer
2020-07-13[spec] Specify execution order of side-effect-having statements (#1724)Albert Magyar
2020-07-09[spec] Explicitly disallow shadowing of component names (#1749)Albert Magyar
2020-06-23Basic model checking API (#1653)Tom Alcorn
2020-05-18Fix typo in spec description of 'tail' (#1626)Albert Magyar
2020-05-11spec: Ran `aspell` on `spec.tex`. (#1564)Alberto Gonzalez
2020-05-06Update spec.pdfSchuyler Eldridge
2020-05-06Clarify spec indentation of when/elseSchuyler Eldridge
2020-05-06Clarify indentation in specSchuyler Eldridge
2020-04-13[spec] Add Fixed to spec (#1456)Albert Magyar
2020-03-26Update spec to clarify sign and use 'h' for hex throughoutAlbert Magyar
2020-03-13[spec] Update Mid FIRRTL spec to reflect removal of subaccesses (#1451)Albert Magyar
2020-03-02Update single-line when/else example in spec to match implementation (#1414)Albert Magyar
2020-02-24[spec] clarify that div-by-zero is undefined (#1409)Albert Magyar
2020-02-11[spec] Change sub(UInt, UInt) output type to UInt (#1378)Albert Magyar
2020-02-06Add note to spec about reductions on zero-width wiresAlbert Magyar
2020-01-15improve the tail ir usability. (#1241)Sequencer
2019-11-13Add spec for Analog type and attach statement (#1222)Albert Magyar
2019-09-30Define read-write collison for independently clocked mem ports (#1188)Albert Magyar
2019-09-16Update Spec from Gender to FlowSchuyler Eldridge
2019-08-07Check mems for legal latencies; ban zero write latency. (#1147)Albert Magyar
2019-07-30Make write-under-write section for mems in spec (#1140)Albert Magyar
2019-06-03spec: mixed-input arguments for prim ops are no longer allowed (#1085)Kevin Laeufer
2019-03-25Correct a typo in spec.tex (#1063)Felix Yan
2019-01-31Add MidFIRRTL spec (#1003)Albert Magyar
2018-09-27Number all code examples & add specification build to Makefile (#894)Ben Marshall
2018-06-11Fix some typos in leftovers.txt (#822)Felix Yan
2018-03-20Correct extmodule example in spec (#768)Albert Magyar
2018-02-16Update spec for rhsSchuyler Eldridge
2017-12-24Spec erroneously says mod instead of rem.Paul Rigge
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
2016-11-03Updated future release with stricter low firrtlazidar
2016-09-22Fixed width inference for add, sub (#312)Adam Izraelevitz
2016-08-17Change RW port names (#236)Angie Wang
2016-08-16Spec bugfix: update concrete reg syntax example (#233)Adam Izraelevitz
2016-07-27Merge pull request #205 from ucb-bar/add-future-releaseAdam Izraelevitz
2016-07-27Added future-release.txtazidar
2016-07-27Fixed reg concrete syntax. #197.azidar
2016-05-23Updated spec. Changed dshl width to w(e) + 2^w(n) - 1. Changed fileinfo to ju...azidar
2016-02-23Updated pdfazidar
2016-02-09Added license to FIRRTL filesazidar
2016-02-09Added changes that addressed feedback, spec ready for releaseazidar
2016-01-28Changed rmode to wmodeazidar
2016-01-28Changed mod to remazidar
2016-01-28Updated todo listazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-27Reworked readwriter typesazidar
2016-01-25Added verilog rename passazidar
2016-01-25Removed random printlnazidar
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