diff options
| author | azidar | 2016-01-26 14:16:09 -0800 |
|---|---|---|
| committer | azidar | 2016-01-28 09:25:03 -0800 |
| commit | f711861808e3ca914f71a3089c6879dbcb7dc08d (patch) | |
| tree | d7864745eaa8048e6a0a2126c150102dd1b2c864 /spec | |
| parent | 6c2b6ea5e4ec00aae0963402e2565e91e95098ac (diff) | |
Changed register syntax for optional reset and init values
Diffstat (limited to 'spec')
| -rw-r--r-- | spec/spec.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/spec/spec.tex b/spec/spec.tex index 12f2c91e..7c528467 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -1792,7 +1792,6 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio %\section{TODO} % %- FIRRTL implementation -% - Rework readwrite port types ; limits optimizations but probably ok % - Make register reset/init optional ; good % - removed addw, added head and tail ; great! % - Add UBits ; andrew doesn't care, favors overloading UInt @@ -1800,6 +1799,7 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio % - Add partial connect algorithm ; % - Add oriented types to type checker % - Add memory read-under-write flag ; probably overengineering, but could be a wash +% - *FINISHED* Rework readwrite port types ; limits optimizations but probably ok % - *FINISHED* Add Mux expression ; that's lovely, need glitch-free mux for clock types % - *FINISHED* add rename pass for verilog % - *FINISHED* Add is invalid ; good |