From f711861808e3ca914f71a3089c6879dbcb7dc08d Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 26 Jan 2016 14:16:09 -0800
Subject: Changed register syntax for optional reset and init values

---
 spec/spec.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'spec')

diff --git a/spec/spec.tex b/spec/spec.tex
index 12f2c91e..7c528467 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1792,7 +1792,6 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %\section{TODO}
 %
 %- FIRRTL implementation
-%   - Rework readwrite port types       ; limits optimizations but probably ok
 %   - Make register reset/init optional ; good
 %   - removed addw, added head and tail ; great!
 %   - Add UBits                         ; andrew doesn't care, favors overloading UInt
@@ -1800,6 +1799,7 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
 %   - Add partial connect algorithm     ; 
 %   - Add oriented types to type checker
 %   - Add memory read-under-write flag  ; probably overengineering, but could be a wash
+%   - *FINISHED* Rework readwrite port types       ; limits optimizations but probably ok
 %   - *FINISHED* Add Mux expression                ; that's lovely, need glitch-free mux for clock types
 %   - *FINISHED* add rename pass for verilog
 %   - *FINISHED* Add is invalid                    ; good
-- 
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