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authorazidar2016-01-27 11:30:35 -0800
committerazidar2016-01-28 09:25:04 -0800
commit5c1f1c18cae31eb53bf09cb58f6ecd6b30e55fb3 (patch)
tree3bea2b11bab215ca8456badeec129d65ac688a39 /spec
parent5ab30c681558d2a26000696e518ee5b28deb1303 (diff)
Updated todo list
Diffstat (limited to 'spec')
-rw-r--r--spec/spec.tex4
1 files changed, 2 insertions, 2 deletions
diff --git a/spec/spec.tex b/spec/spec.tex
index 7c528467..dc15e1b8 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1792,13 +1792,13 @@ The concrete syntax of FIRRTL is defined in section \ref{syntax_tree}. Productio
%\section{TODO}
%
%- FIRRTL implementation
-% - Make register reset/init optional ; good
-% - removed addw, added head and tail ; great!
% - Add UBits ; andrew doesn't care, favors overloading UInt
% - Add SBits
% - Add partial connect algorithm ;
% - Add oriented types to type checker
% - Add memory read-under-write flag ; probably overengineering, but could be a wash
+% - *FINISHED* Make register reset/init optional ; good
+% - *FINISHED* removed addw, added head and tail ; great!
% - *FINISHED* Rework readwrite port types ; limits optimizations but probably ok
% - *FINISHED* Add Mux expression ; that's lovely, need glitch-free mux for clock types
% - *FINISHED* add rename pass for verilog