Add note to spec about reductions on zero-width wires

2 files changed, 2 insertions, 0 deletions

diff --git a/spec/spec.pdf b/spec/spec.pdf
index 8b7fd125..e49441ad 100644
--- a/spec/spec.pdf
+++ b/spec/spec.pdf
diff --git a/spec/spec.tex b/spec/spec.tex
index 68a404a8..a8a40da4 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -1533,6 +1533,8 @@ andr,orr,xorr & (e)  & () & (UInt) & UInt & 1\\
 
 The bitwise reduction operations correspond to a bitwise and, or, and exclusive or operation, reduced over every bit in \vv{e}.
 
+In all cases, the reduction incorporates as an inductive base case the ``identity value'' associated with each operator. This is defined as the value that preserves the value of the other argument: one for \vv{and} (as $x \wedge 1 = x$), zero for \vv{or} (as $x \vee 0 = x$), and zero for \vv{xor} (as $x \oplus 0 = x$). Note that the logical consequence is that the and-reduction of a zero-width expression returns a one, while the or- and xor-reductions of a zero-width expression both return zero.
+
 \subsection{Concatenate Operation}
 
 \begin{figure}[H]