diff options
| author | Kevin Laeufer | 2020-07-15 12:21:26 -0700 |
|---|---|---|
| committer | GitHub | 2020-07-15 19:21:26 +0000 |
| commit | 24be0ac3121e8f5d7b4bf8d6247e305ed0f0a656 (patch) | |
| tree | 9acbdf85c86985921a84fa329838062a78e71588 /spec | |
| parent | 005a3d1644742029e744a64c2d9c452969bc64ff (diff) | |
ir: store FileInfo string in escaped format (#1690)
This should speed up the common case
as the compiler never operates on the
unescaped string.
The new escape function also fixes a bug
where ']' was not escaped even though it
is the delimiting character for FileInfo.
In order to maintain backwards
compatibility for the ProtoBuf format,
this patch adds escape/unescape calls
when going from/to protobuf format.
For better performance we should consider
changing the protobuf format.
Diffstat (limited to 'spec')
| -rw-r--r-- | spec/spec.pdf | bin | 330256 -> 338195 bytes | |||
| -rw-r--r-- | spec/spec.tex | 27 |
2 files changed, 15 insertions, 12 deletions
diff --git a/spec/spec.pdf b/spec/spec.pdf Binary files differindex 26be49e6..fa3dbe8f 100644 --- a/spec/spec.pdf +++ b/spec/spec.pdf diff --git a/spec/spec.tex b/spec/spec.tex index d65078bc..8410c9d2 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -2044,23 +2044,26 @@ circuit Foo : b <= not(a) \end{lstlisting} -All circuits, modules, ports and statements can optionally be followed with the info token \verb|@[fileinfo]| where fileinfo is a string containing the source file information from where it was generated. +All circuits, modules, ports and statements can optionally be followed with the info token \verb|@[fileinfo]| +where fileinfo is a string containing the source file information from where it was generated. +The following characters need to be escaped with a leading `\verb|\|': +`\verb|\n|' (new line), `\verb|\t|' (tab), `\verb|]|' and `\verb|\|' itself. The following example shows the info tokens included: \begin{lstlisting} -circuit Top : @["myfile.txt: 14, 8"] - module Top : @["myfile.txt: 15, 2"] - output out:UInt @["myfile.txt: 16, 3"] - input b:UInt<32> @["myfile.txt: 17, 3"] - input c:UInt<1> @["myfile.txt: 18, 3"] - input d:UInt<16> @["myfile.txt: 19, 3"] - wire a:UInt @["myfile.txt: 21, 8"] - when c : @["myfile.txt: 24, 8"] - a <= b @["myfile.txt: 27, 16"] +circuit Top : @[myfile.txt 14:8] + module Top : @[myfile.txt 15:2] + output out:UInt @[myfile.txt 16:3] + input b:UInt<32> @[myfile.txt 17:3] + input c:UInt<1> @[myfile.txt 18:3] + input d:UInt<16> @[myfile.txt 19:3] + wire a:UInt @[myfile.txt 21:8] + when c : @[myfile.txt 24:8] + a <= b @[myfile.txt 27:16] else : - a <= d @["myfile.txt: 29, 17"] - out <= add(a,a) @["myfile.txt: 34, 4"] + a <= d @[myfile.txt 29:17] + out <= add(a,a) @[myfile.txt 34:4] \end{lstlisting} \section{FIRRTL Language Definition} |
