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This is necessary for user-defined Record-derived types to retain
the same signal name as they would using a Vec.
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* change builder for bundle reflection fix
* fixed bug -- should be not assignable
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withClockAndReset, withReset, and withClock allow changing the implicit clock and reset.
Module.clock and Module.reset provide access to the current implicit clock and reset.
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Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
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Fix default suggested name of Module instances (now based on desired name
rather than actual assigned name).
Remove parent/child relationship from Namespace.
Previously, Module and Bundle namespaces were "children" of the Module
definition namespace. This could lead to collisions that would give unexpected
names for module instances or Bundle elements. In particular, otherwise
identical modules that instantiate other identical modules in such a way that
the instance cannot be named via reflection would not be deduplicated because
the names of the instances would collide with the names of the modules in the
Builder.globalNamespace.
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* Name propagation
* chiselName everywhere at best-effort level
* Better collision handling
* Allow recursing into inner anonymous functions
* Add for loop and anonymous inner function tests
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Record gives uses the power to create collections of heterogenous elements.
Bundle is a special case of Record that uses reflection to populate the
elements of the collection. Bundle also attempts to implement cloneType whereas
users of Record are required to supply one.
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* Support for creating chisel annotations that are consumed by firrtl
Update annotation serialization in Driver
Add DiamondAnnotation Spec that illustrates how to do simple annotations
frontEnd must have dependency on firrtl
Add annotation method to Module
Circuit has extra optional parameter that is Seq of Annotations
In Builder add annotation buffer to DynamicContext to store annotations created in modules
Added explicit types on naming api methods to avoid type confusion
Because some names are not available until elaboration create intermediate ChiselAnnotation that
gets turned into a firrtl Annotation after elaboration
In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though
intermediate file .fir and .anno files are still created for inspection and/or later use
* Somehow missed ChiselAnnotation
* fixes for Jack's review of PR
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Remove modName from Module
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Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.
Resolves #289
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Implemented by adding a Boolean to check for alternating invocations of object
Module.apply and the constructor of abstract class Module.
Fixes #192
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Add a Builder.exception() method for those cases where continuing is likely to mask the initial error.
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No more need for e.g.
new Bundle {
def foo(dummy: Int): Data
}
as now you can write
new Bundle {
def foo: Data
}
This also removes code duplication with Module.
h/t @sdtwigg
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* FixedPoint number support for chisel3
FixedPoint numbers have a width and a binary position
Either, neither or both maybe inferred.
Firrtl will convert these to SInts during lowering passes
* Fixes based on Jack's comments on PR #328
* Add experimental warning to FixedPoint class and object
* Fixed comment per Adam's comment on PR #328
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Code that imports Chisel._ shouldn't see them.
Not sure if requireIOWrap is the right condition... or if cyan is a
good choice of color for deprecation warnings.
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Massage CompileOption names in an attempt to preserve default (Strict) CompileOptions in the absence of explicit imports.
NOTE: Since the default is now strict, we may encounter errors when we generate connections for clients (i.e., in Vec.do_apply() when we wire up a sequence).
We should really thread the CompileOptions through the macro system so the client's implicits are used.
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Additionally, fix Clock.asUInt (previously, it threw an esoteric exception), and add a simple test of both.
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In the Chisel frontend, the implicit clock is named clock, but in the
generated FIRRTL, it is named clk. There is no reason for this
discrepancy, and yet fixing it is painful, as it will break test harnesses.
Better to take the pain now than later.
Resolves #258.
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Printable is a new type that changes how printing of Chisel types is represented
It uses an ordered collection rather than a format string and specifiers
Features:
- Custom String Interpolator for Scala-like printf
- String-like manipulation of "hardware strings" for custom pretty-printing
- Default pretty-printing for Chisel data types
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Eliminate builder compileOptions.
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Stricter values are "true". Current default (not strict) values are "false".
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signalName -> instanceName
SignalId -> InstanceId
Based on Stephen's comments on PR
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"assumeNoDirectionIsInput".
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* signalName: returns the chirrtl name of the signal
* pathName: returns the full path name of the signal from the top module
* parentPathName: returns the full path of the signal's parent module instance from the top module
* parentModName: returns the signal's parent **module(not instance)** name.
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Revive support for firrtl flip direction.
Remove compileOptions.internalConnectionToInputOk
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Assume LHSItOutput if neither side is driving.
Restore Wire()'s removal of direction in binding.
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Nothing uses these now, but when we integrate Stephen's PR200, we'll need a way to selectively enable some strict connection checks on a file by file basis. We plan to do this using package imports which will define suitable compilation options.
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It's not entirely clear what the FIRRTL implementation supports, so
I'm using the ANSI C requirements for the time being.
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