Merge branch 'master' into gsdt

1 files changed, 1 insertions, 17 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 64d7d5fd..1f05b6e2 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -169,22 +169,6 @@ case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Comm
 case class Stop(sourceInfo: SourceInfo, clk: Arg, ret: Int) extends Command
 case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg
 case class Port(id: Data, dir: Direction)
-case class Printf(sourceInfo: SourceInfo, clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command {
-  require(formatIn.forall(c => c.toInt > 0 && c.toInt < 128), "format strings must comprise non-null ASCII values")
-  def format: String = {
-    def escaped(x: Char) = {
-      require(x.toInt >= 0)
-      if (x == '"' || x == '\\') {
-        s"\\${x}"
-      } else if (x == '\n') {
-        "\\n"
-      } else {
-        require(x.toInt >= 32) // TODO \xNN once FIRRTL issue #59 is resolved
-        x
-      }
-    }
-    formatIn.map(escaped _).mkString
-  }
-}
+case class Printf(sourceInfo: SourceInfo, clk: Arg, pable: Printable) extends Command
 
 case class Circuit(name: String, components: Seq[Component])