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authorJim Lawson2016-08-18 15:26:39 -0700
committerJim Lawson2016-08-18 15:26:39 -0700
commit471a9e2d15d4c968fc6eca9a86c232c6c9c9322d (patch)
treeb9c30d372884ab2e7c8f28bd9bde58443a1b2dd4 /chiselFrontend/src/main/scala/chisel3/internal
parentbd6e69c19aef76b6e87f7e328e03d1b93f8a1472 (diff)
Add assumeNoDirectionIsOutput.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
index e040201b..912184fb 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
@@ -19,4 +19,5 @@ class CompileOptions(optionsMap: Map[String, String]) {
val portDeterminesDirection: Boolean = optionsMap.getOrElse("portDeterminesDirection", looseDefault).toBoolean
val tryConnectionsSwapped: Boolean = optionsMap.getOrElse("tryConnectionsSwapped", looseDefault).toBoolean
val assumeLHSIsOutput: Boolean = optionsMap.getOrElse("assumeLHSIsOutput", looseDefault).toBoolean
+ val assumeNoDirectionIsOutput: Boolean = optionsMap.getOrElse("assumeNoDirectionIsOutput", looseDefault).toBoolean
}