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* Rename coreMacros to macros
* Rename chiselFrontend to core
Also make each subproject publish with "chisel3-" as a prefix
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* Remove toNamed (and friends) deprecation.
* Add inadvertently deleted leading double quote.
* Remove commented out deprecations.
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Add trait chisel3.experimental.NoChiselNamePrefix which causes
@chiselName to skip naming of the instance effectively preventing it
from prefixing any vals inside the instance. It can be applied to
classes such that all instances of that class have this property, or to
individual instances (via creating an anonymous class inline).
Also add basic ScalaDoc for NoChiselNamePrefix and chiselName.
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Change the logic for determining which nested ChiselException cause to
use for a trimmed stack trace. Previously, this would use the
outermost. This commit changes this to use the innermost.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Change ChiselException.builderName to compute the name of Chisel's
internal Builder as opposed to hard-coding this with a string.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Changes the behavior of ChiselException stack trace trimming to use
either the first exception that includes a method from the Builder or
the outer exception.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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Change the emission strategy for Bits methods andR and orR to emit
FIRRTL bitwise reduce operations andr and orr.
Add two tests that assert the correct behavior of these operations in
BitwiseOpsSpec.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Add support for readUnderWrite to SyncReadMem
* Add write collision behavior test to MemorySpec
* Update constant names
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Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: Chick Markley <chick@qrhino.com>
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materialized all values
- Fixed computation in getHighestPossibleValue, erroneously was using lower intead of upper
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Plan to be released with 3.3.
Breaks experimental Range API.
Adds new Interval type and associated support.
This commit adds the following:
- Renamed Range to IntervalRange to avoid name collision with scala Range
- Changed RangeTransform macro to Return an IntervalRange
- Improved error messages on missing comma or decimal
- Added notational support for binary point
- Some formatting cleanup also
- SIntFactory
- Change to use IntervalRange API
- UIntFactory
- UInt from range has custom width computation
- It does not need to deal with lowerbound extending bit requirements
- Code to handle special case of range"[0,0]" to have a width of 1
- IR.scala
- Removed Bound and other constraint code that was duplicating firrtl stuff
- Added new RangeType
- Added IntervalRange class and object
- RangeSpec
- modified just a bit to handle notational differences
- previous range interpolator returned tuple now returns IntervalRange
- Add IntervalType to emitter
- Added IntervalSpec with many tests
- Added ScalaIntervalSimulatorSpec which tests golden model for Interval
- Added ScalaIntervalSimulator which is a golden model for Interval
- This gold may not have been polished to a high sheen
- Add IntervalLit cases to Converter
- Add Interval PrimOps to IR
- asInterval, wrap, squz, clip, setp, decp, incp
- Add IntervalLit class to IR
- Add Interval to MonoConnect
- Add Interval Type to Bits (in experimental package)
- add conversions to Interval from other types
- Add Interval clone stuff to Data
- Add Literal creation helpers to chisel3 package
- these may move to experimental if I can figure that out
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* Move dontTouch out of experimental package.
* Move RawModule, MultiIOModule out of experimental.
* Respond to comments - Move LagacyModule from experimental to internal.
*NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions.
* Fix up a few more imports.
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Adds new AsyncReset and "abstract" Reset types. Reset is inferred
in FIRRTL to be either AsyncReset or Bool. The "reset type" of a
register is set by the type of its reset signal:
val asyncReset: AsyncReset = IO(Input(AsyncReset()))
val syncReset: Bool = IO(Input(Bool()))
val abstractReset: Reset = IO(Input(Reset()))
val asyncReg = withReset(asyncReset) { RegInit(0.U) }
val syncReg = withReset(syncReset) { RegInit(0.U) }
val inferredReg = withReset(abstractReset) { RegInit(0.U) }
AsyncReset can be cast to and from Bool. Whereas synchronous reset is
equivalent to a mux in front of a flip-flop and thus can be driven by
logic, asynchronous reset requires that the reset value is a constant.
This is checked in FIRRTL.
Inference of the concrete type of a Reset occurs based on the type the
Reset's drivers. This inference is very simple, it is simple forward propagation
of the type, but it allows for writing blocks and modules that are agnostic
to the reset type. In particular, the implicit `reset` value in MultiIOModule
and thus Module is now concretely an instance of Reset and thus will be
inferred in FIRRTL.
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Added Aspects to Chisel, enabling a mechanism for dependency injection to hardware modules.
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Short-term patch to enable this useful behavior. In the future, we may want to rearchitect the type system and/or rethink the more edge-case connect behavior.
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* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
* Move Aggregate, Clock, Mem, Printf, Reg
* Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
* Revive core package object to provide aliases for moved definitions.
* Cleanup package definitions; eliminate ambiguous implicits
* Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
* Put BitPat back in chisel3.util
* More experimental motion - avoid multiple import definitions.
* Add experimental.FixedPoint alias
* Add EnumType definition to core package.
Update deprecated messages to refer to correct object
* Move FixedPoint into the experimental package (but keep it in Bits.scala).
* Add missing implicits to core/package - compatibility
* Cleanup: update ScalaDoc references; remove unused imports
* Add Reset alias to core/package
* Use common 3.2 version in deprecation warning
* Move Binding from core to internal.
* Optimize imports.
* Repair IntelliJ's overly cleanliness.
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
* Change == to reference equality (eq) in Data print (#1044)
* Remove @chiselName from MixedVec (#1045)
* Fix enum annotations (#936)
* Turned off strong enum annotations because they weren't working with Vec
indexes
* Add new EnumVecAnnotation for vecs of enums and vecs of bundles with
enum fields
* Changed Clock's width parameter back to a fixed constant value of 1
* Fixed enum annotations for Vecs of Bundles which contain enum elements
* Fixed usage of "when/otherwise" to use consistent style
* Add Record to type hierarchy documentation
* Undeprecate isLit (#1048)
* move doNotDedup to experimental (#1008)
* Aggregate coverage - aggregate tests but not publishing (#1040)
Discover a working combination of aggregate usage to enable coverage of subproject testing but publish a single Jar.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
This should finally fix #772.
* Check field referential equality in autoclonetype (#1047)
* Allow naming annotation to work outside builder context (#1051)
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Make core.DontCare private to chisel3 (#1054)
Force clients to access 'DontCare' through the chisel3 package to ensure it's created as a chisel3 object and not a client object.
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Detect bundle aliasing (#1050)
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Optimize imports.
* Move Analog to experimental.
* More repackage cleanup - reduce differences with master.
* Cleanup chisel3 references.
* More chisel3 reference cleanup.
* Merge cleanup.
* Remove unused import
* Bump core deprecation to 3.3
* Move DontCare back into Data.scala inside package internal
* Re-indent experimental/internal package code
* Move code back to original files - facilitate comparison with other branches
* Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
* More master diff minimization.
* Try to eliminate JVM hang due to static initialization deadlock (#1053)
* Ignore empty aggregates elements when binding aggregate direction (#946)
Previously, including an empty aggregate in a Bundle would cause
a MixedDirectionAggregateException because it has no elements and thus
doesn't have a direction
* Add SampleElementBinding for Vec sample elements
* Add ActualDirection.Empty for bound empty aggregates
* Implement connectFromBits in ChiselEnum (#1052)
This is necessary to use ChiselEnum in aggregates where things are
casted using .asTypeOf
* Move Analog to experimental.
More repackage cleanup - reduce differences with master.
Cleanup chisel3 references.
More chisel3 reference cleanup.
* Fix wrong directionality for Vec(Flipped())
Create Chisel IR Port() in a way that Converter is happy with.
Also add more extensive test suite for future-proofing.
Close #1063
* Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Put BitPat back in chisel3.util
More experimental motion - avoid multiple import definitions.
Add experimental.FixedPoint alias
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Add Reset alias to core/package
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Repair IntelliJ's overly cleanliness.
Move Bits, Data, and BitPat to chiselFrontend/src/main/scala/chisel3
and deal with the subsequent fallout.
Move Aggregate, Clock, Mem, Printf, Reg
Move almost all chisel3.core definitions to chisel3 or chisel3.experimental
Revive core package object to provide aliases for moved definitions.
Cleanup package definitions; eliminate ambiguous implicits
Move more definitions to experimental.
Extract BaseModule, DataMirror, ExtModule, IO into their own files.
Add EnumType definition to core package.
Update deprecated messages to refer to correct object
Move FixedPoint into the experimental package (but keep it in Bits.scala).
Add missing implicits to core/package - compatibility
Cleanup: update ScalaDoc references; remove unused imports
Use common 3.2 version in deprecation warning
Move Binding from core to internal.
Optimize imports.
Merge cleanup.
Remove unused import
Bump core deprecation to 3.3
Move DontCare back into Data.scala inside package internal
Re-indent experimental/internal package code
Move code back to original files - facilitate comparison with other branches
Some code motion, update imports, minimize master differences
Move exceptions up to chisel3 package object - they're part of the interface.
More master diff minimization.
Fix minor discrepancies with repackagecore-testbed
* Remove redundant imports
As part of its import updating process, IntelliJ converted some import statements to `import package.{object, _}`. Is this intended to show an explicit dependency on `package.object` and a further dependency on `package` implicits? Unsure. Replace these with `import package._`
* Move the BaseModule object into the internal package.
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* RawModule with no reset should be able to use withClock method.
- refactor ClockAndReset
- now has `clockOpt: Option[Clock]` and `resetOpt: Option[Reset]` constructor params
- convenience methods clock and reset tries to deref the option
- ClockAndReset.empty is factory method for (None, None)
- In Builder
- forcedClock does not check resetOpt now
- forcedReset does not check clockOpt now
- withClock no longer looks at resetOpt
- withReset no longer looks at clockOpt
- Module starts with empty ClockAndReset
* RawModule with no reset should be able to use withClock method.
Refactor again based on @ducky64 comments
- refactor away ClockAndReset, now builder just has a
- currentClock
- currentReset
- withClock, withRest, withClockAndReset just use these fields directly
* RawModule with no reset should be able to use withClock method.
- Fixed typo in withReset handler, now picks up new reset
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- Introduce internal helper `castToInt`, which issues an error when the input
BigInt can't be represented as Int.
- Use `castToInt` wherever we were using `toInt` in a potentially unsafe way.
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* Update style warnings now that subprojects are aggregated.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
* Remove bogus tests that crept in with git add
* Add missing import.
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Module class names (#994)
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- Trim stack trace to show better, reduced information to the user
- Add --full-stacktrace to FIRRTL option to show full stack trace
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* Added new strongly-typed enum construct called "StrongEnum". "StrongEnum" will automatically generate annotations that HDL backends can use to mark components as enums
Removed "override val width" constructor parameter from "Element" so that classes with variable widths, like the new strong enums, can inherit from it
Changed the parameter types of certain functions, such as "switch", "is", and "LitArg.bindLitArg" from "Bits" to "Element", so that they can take the new strong enums as arguments
* Added tests for the new strong enums
* Changed StrongEnum exception names and made sure in StrongEnum tests that the correct types of exceptions are thrown
* Fixed bug where an enum's global annotation would not be set if it was used in multiple circuits
Made styling changes to StrongEnum.scala
* Reverted accidental changes to the AnnotatingDiamond test
* Changed the API for casting non-literal UInts to enums
Added an isValid function that checks whether or not enums have valid values
Calling getWidth on an enum's companion object now returns a BigInt instead of an Int
* Casting a literal to an enum using the StrongEnum.castFromNonLit(n) function is now simply a wrapper for StrongEnum.apply(n)
* Fixed compilation bug
* * Added "next" method to EnumType
* Renamed "castFromNonLit" to "fromBits"
* The FSM example in the test/scala/cookbook now uses StrongEnums
* * Changed strong enum API, so that users no longer have to declare both a class and a companion object for each strong enum
* Strong enums do not have to be static any longer
* * Added scope protections to ChiselEnum.Value so that users cannot call it
outside of a ChiselEnum definition
* Renamed ChiselEnum.Value type to ChiselEnum.Type so that we can give
it a companion object just like UInt and Bool do
* * Moved strong enums into experimental package
* Non-literal UInts can now be cast to enums with apply() rather than
fromBits()
* Reduced code-duplication by moving some functions from EnumType and
Bits to Element
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Fixes #852
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Add chisel3.experimental.IO for programmatic port creation in Raw and
MultiIOModules. suggestName is required to name ports that cannot be
named by reflection. Two ports cannot be given the same name.
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Makes Builder.updateBundleStack a bit stricter in deciding how many stack frames to discard by additionally matching against method names and deleting stack frames at or above the frame currently being inserted.
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* Generalize ChiselAnnotation
This allows us to delay creation of Annotations till elaboration is
complete. Also update all annotation-related code.
* Add RunFirrtlTransform
Use a Chisel-specific RunFirrtlTransform API to preserve behavior of old
ChiselAnnotation (now called ChiselLegacyAnnotation)
* Use unique test directories in ChiselRunners.compile
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It appears #754 breaks more code than I thought, so this makes it a soft error (with a runtime deprecation warning - to get people to fix their stuff before we break it for real) for now.
This additionally changes the autoclonetype errors to be more deterministic (reporting class names instead of object names) in the most common cases, to allow the deprecations manager to deduplicate warnings.
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* Better support for autoclonetype of nested Bundles
* Move bundleStack to dynamicContext
* prefer $outer if available, make guesses distinct
* Catch IllegalAccessException in autoclonetype
In strange circumstances this type of exception can occur when accessing $outer
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Add runtime warnings for use of deprecated Chisel methods. This is done using a macro that takes the message from a `@deprecated` annotation, and adds a call to `Builder.deprecated`.
Reasoning is that by default, Scala doesn't print all deprecations, and that it's somewhat tricky to notice them - yet some support questions revolve around the use of deprecated and terribad API. This now prints warnings for uses of deprecated functions at runtime, and aggregates them by error and line to avoid spam. Also included is convenient information on enabling scalac deprecations.
This also changes how line numbers for Chisel's error facility is determined, using prefix string comparison of the stack trace element classnames, instead of checking if the class is a subtype of UserModule. The previous one (specifically, calls to Class.forName) seems to interact badly with reflection-based cloneType when called at scale. This should also give more accurate reporting of errors that are in user code but outside of a UserModule.
It turns out that `@deprecated` on macro functions don't do anything, so this changes the tags to the functions that the macros point to, which seems to work properly. It also turns out that there's a bunch of uses of deprecated functions in chiselTests which needs to be fixed.
Not all `@deprecated` functions are also annotated with `@chiselRuntimeDeprecation`, because they're still used in Chisel internals, and we can't track whether they're called by the user or by Chisel and it will give a misleading error. These are a small amount of functions.
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Disambiguate DontCare reference in initializeSingletons() avoiding compilation error during unidoc generation.
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* Require explicit connection to DontCare to generate "is invalid".
* Add tests for RefNotInitializedException.
Currently, we fail the when ... otherwise ...
* Disable ScalaTest shrinking on error in ComplexAssignSpec.
* fix broken merge; still some binding issues
* cleanup DontCare connection checks; add missing directions to test module IOs
* Have library code inherit compileOptions from the enclosing Module (if it exists).
* work around current firrtl uninitialized references with Strict compile options and explicitInvalidate
* more CompileOptions cleanup; move test-specific defines to package object
* minimize differences with master
* set default CompileOptions.explicitInvalidate to false until we fix the FIRRTL when issue
* ignore the StrictCompiler property checks (until CompileOptions.explicitInvalidate is defaulted to true)
* Revert "more CompileOptions cleanup; move test-specific defines to package object"
This reverts commit e4486edcba990d150e76e08a2fc6abca033556e0.
* Revert "work around current firrtl uninitialized references with Strict compile options and explicitInvalidate"
This reverts commit 426faa430a62c3dac2dbdf33044d3386d4243157.
* remove unused code
* Convert to binding-based DontCare implementation
* comment cleanup to minimize differences with master
* Tentatively remove possibly redundant DefInvalid on module ports.
* Respond to code review change request.
- backout build.sbt change
- correct indentation
- handle bulk of DontCare semantics in elemConnect()
- have DontCare extend Element, not Data (eliminate most Object specific methods
- add comments indicating reason for explicit DontCare connections
* Initialize test elements without requiring a DontCare.
* Respond to review change requests.
- DontCare should work on left or right side in BiDirectional connections
- call bind() to set DontCare binding instead of messing with internal variables
- DontCares are only equivalent with DontCares
- clean up processWhens() definition
* Eliminate DontCare connection to inputs in MonoConnect().
* Pull aggregates apart for the purpose of DontCare connections.
* Restore the explicit (conditionally executed) ports DefInvalidin ImplicitModule()
* Don't add DontCare's to the module list of _ids.
* Add missing DefInvalid() to LegacyModule().
* Respond to review requests: add DontCare BiConnect Vec, remove null parent hack to avoid addId(), initialize singletons early in Builder
* Move DontCare out of chisel3.experimental.
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Preprocess chisel3 IR before emission to determing whether
whens have alternatives.
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Bool implements Reset. Compatibility package includes an implicit
conversion from Reset to Bool.
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Part 1 of mega-change in #578
Major notes:
- Input(...) and Output(...) now (effectively) recursively override their elements' directions
- Nodes given userDirection (Input, Output, Flip - what the user assigned to _that_ node) and actualDirection (Input, Output, None, but also Bidirectional and BidirectionalFlip for mostly Aggregates), because of the above (since a higher-level Input(...) can override the locally specified user direction).
- DataMirror (node reflection APIs) added to chisel3.experimental. This provides ways to query the user given direction of a node as well as the actual direction.
- checkSynthesizable replaced with requireIsHardware and requireIsChiselType and made available in chisel3.experimental.
Internal changes notes:
- toType moved into Emitter, this makes the implementation cleaner especially considering that Vec types can't be flipped in FIRRTL. This also more clearly separates Chisel frontend from FIRRTL emission.
- Direction separated from Bindings, both are now fields in Data, and all nodes are given hierarchical directions (Aggregates may be Bidirectional). The actualDirection at the Element (leaf) level should be the same as binding directions previously.
- Bindings are hierarchical, children (of a, for example, Bundle) have a ChildBinding that points to their parent. This is different than the previous scheme where Bindings only applied at the Element (leaf) level.
- Lots of small misc clean up.
Future PRs will address other parts of #578, including stricter direction checks that aren't a side-effect of this internal refactor, stricter checks and splitting of binding operations (Wire vs. WireInit), and node operations not introduced here (getType and deprecation of chiselCloneType). Since those shouldn't mess with internals, those should be much smaller.
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