diff options
| author | Albert Magyar | 2020-02-03 13:42:39 -0700 |
|---|---|---|
| committer | GitHub | 2020-02-03 13:42:39 -0700 |
| commit | 509895c428f73b1c47e018df33e6cb64834e6e94 (patch) | |
| tree | e2912c1c7528df820fe9163272397edd7efa1259 /chiselFrontend/src/main/scala/chisel3/internal | |
| parent | 4f1f638663a7176ac28d95d71c14a37021314c3b (diff) | |
Add read-under-write parameter to SyncReadMem (#1183)
* Add support for readUnderWrite to SyncReadMem
* Add write collision behavior test to MemorySpec
* Update constant names
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/Converter.scala | 4 | ||||
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 4 |
2 files changed, 5 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/Converter.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/Converter.scala index 548ed294..5c1d6935 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -106,8 +106,8 @@ private[chisel3] object Converter { convert(reset, ctx), convert(init, ctx))) case e @ DefMemory(info, id, t, size) => Some(firrtl.CDefMemory(convert(info), e.name, extractType(t), size, false)) - case e @ DefSeqMemory(info, id, t, size) => - Some(firrtl.CDefMemory(convert(info), e.name, extractType(t), size, true)) + case e @ DefSeqMemory(info, id, t, size, ruw) => + Some(firrtl.CDefMemory(convert(info), e.name, extractType(t), size, true, ruw)) case e: DefMemPort[_] => Some(firrtl.CDefMPort(convert(e.sourceInfo), e.name, fir.UnknownType, e.source.fullName(ctx), Seq(convert(e.index, ctx), convert(e.clock, ctx)), convert(e.dir))) diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index e76a8d60..a16d84bb 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -2,6 +2,8 @@ package chisel3.internal.firrtl +import firrtl.{ir => fir} + import chisel3._ import chisel3.internal._ import chisel3.internal.sourceinfo.SourceInfo @@ -721,7 +723,7 @@ case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition -case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition +case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition case class DefInstance(sourceInfo: SourceInfo, id: BaseModule, ports: Seq[Port]) extends Definition case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command |