diff options
| author | Jim Lawson | 2019-09-11 09:09:05 -0700 |
|---|---|---|
| committer | GitHub | 2019-09-11 09:09:05 -0700 |
| commit | 3d65ccee36fd97c26d170f631322ad0c2c9d6dd7 (patch) | |
| tree | 45b40cd34f1e3f8927017608a503d0011bb74b5e /chiselFrontend/src/main/scala/chisel3/internal | |
| parent | cafc46863dc2c26c3ee38eb507a5c3d6ff60d4b5 (diff) | |
Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)
* Move dontTouch out of experimental package.
* Move RawModule, MultiIOModule out of experimental.
* Respond to comments - Move LagacyModule from experimental to internal.
*NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions.
* Fix up a few more imports.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
4 files changed, 4 insertions, 4 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala index f49deff4..6b4c1070 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala @@ -3,7 +3,7 @@ package chisel3.internal import chisel3._ -import chisel3.experimental.{Analog, BaseModule, RawModule, attach} +import chisel3.experimental.{Analog, BaseModule, attach} import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{Connect, DefInvalid} import scala.language.experimental.macros diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Binding.scala b/chiselFrontend/src/main/scala/chisel3/internal/Binding.scala index 23e35f5c..07c44f9f 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Binding.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Binding.scala @@ -3,7 +3,7 @@ package chisel3.internal import chisel3._ -import chisel3.experimental.{BaseModule, RawModule} +import chisel3.experimental.BaseModule import chisel3.internal.firrtl.LitArg /** Requires that a node is hardware ("bound") diff --git a/chiselFrontend/src/main/scala/chisel3/internal/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/internal/MonoConnect.scala index ace7be20..1c001183 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/MonoConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/MonoConnect.scala @@ -3,7 +3,7 @@ package chisel3.internal import chisel3._ -import chisel3.experimental.{Analog, BaseModule, EnumType, FixedPoint, RawModule, UnsafeEnum} +import chisel3.experimental.{Analog, BaseModule, EnumType, FixedPoint, UnsafeEnum} import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{Connect, DefInvalid} import scala.language.experimental.macros diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index e4b660dd..4643f66c 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -5,7 +5,7 @@ package chisel3.internal.firrtl import chisel3._ import chisel3.internal._ import chisel3.internal.sourceinfo.SourceInfo -import chisel3.experimental.{BaseModule, ChiselAnnotation, Param, RawModule} +import chisel3.experimental.{BaseModule, ChiselAnnotation, Param} // scalastyle:off number.of.types |