diff options
46 files changed, 133 insertions, 145 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/Annotation.scala index ec000d93..e54b1bf9 100644 --- a/chiselFrontend/src/main/scala/chisel3/Annotation.scala +++ b/chiselFrontend/src/main/scala/chisel3/Annotation.scala @@ -3,7 +3,7 @@ package chisel3.experimental import scala.language.existentials -import chisel3.internal.{Builder, InstanceId} +import chisel3.internal.{Builder, InstanceId, LegacyModule} import chisel3.{CompileOptions, Data} import firrtl.Transform import firrtl.annotations._ @@ -21,7 +21,7 @@ trait ChiselAnnotation { /** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this Annotation is present * during a run of - * [[Driver$.execute(args:Array[String],dut:()=>chisel3\.experimental\.RawModule)* Driver.execute]]. + * [[Driver$.execute(args:Array[String],dut:()=>chisel3\.RawModule)* Driver.execute]]. * Automatic Transform instantiation is *not* supported when the Circuit and Annotations are serialized before invoking * FIRRTL. */ @@ -45,40 +45,6 @@ object annotate { // scalastyle:ignore object.name } } -/** Marks that a signal should not be removed by Chisel and Firrtl optimization passes - * - * @example {{{ - * class MyModule extends Module { - * val io = IO(new Bundle { - * val a = Input(UInt(32.W)) - * val b = Output(UInt(32.W)) - * }) - * io.b := io.a - * val dead = io.a +% 1.U // normally dead would be pruned by DCE - * dontTouch(dead) // Marking it as such will preserve it - * } - * }}} - * - * @note Calling this on [[Data]] creates an annotation that Chisel emits to a separate annotations - * file. This file must be passed to FIRRTL independently of the `.fir` file. The execute methods - * in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically. - */ -object dontTouch { // scalastyle:ignore object.name - /** Marks a signal to be preserved in Chisel and Firrtl - * - * @note Requires the argument to be bound to hardware - * @param data The signal to be marked - * @return Unmodified signal `data` - */ - def apply[T <: Data](data: T)(implicit compileOptions: CompileOptions): T = { - if (compileOptions.checkSynthesizable) { - requireIsHardware(data, "Data marked dontTouch") - } - annotate(new ChiselAnnotation { def toFirrtl = DontTouchAnnotation(data.toNamed) }) - data - } -} - /** Marks that a module to be ignored in Dedup Transform in Firrtl pass * * @example {{{ @@ -119,7 +85,7 @@ object dontTouch { // scalastyle:ignore object.name object doNotDedup { // scalastyle:ignore object.name /** Marks a module to be ignored in Dedup Transform in Firrtl * - * @param data The module to be marked + * @param module The module to be marked * @return Unmodified signal `module` */ def apply[T <: LegacyModule](module: T)(implicit compileOptions: CompileOptions): Unit = { diff --git a/chiselFrontend/src/main/scala/chisel3/Attach.scala b/chiselFrontend/src/main/scala/chisel3/Attach.scala index 1ceba7c2..25c83d9a 100644 --- a/chiselFrontend/src/main/scala/chisel3/Attach.scala +++ b/chiselFrontend/src/main/scala/chisel3/Attach.scala @@ -2,6 +2,7 @@ package chisel3.experimental +import chisel3.RawModule import chisel3.internal._ import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl._ diff --git a/chiselFrontend/src/main/scala/chisel3/Module.scala b/chiselFrontend/src/main/scala/chisel3/Module.scala index a6f682a8..cd6bbeb8 100644 --- a/chiselFrontend/src/main/scala/chisel3/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/Module.scala @@ -121,7 +121,7 @@ package experimental { } package internal { - import chisel3.experimental.{BaseModule, MultiIOModule} + import chisel3.experimental.BaseModule object BaseModule { private[chisel3] class ClonePorts (elts: Data*)(implicit compileOptions: CompileOptions) extends Record { diff --git a/chiselFrontend/src/main/scala/chisel3/ModuleAspect.scala b/chiselFrontend/src/main/scala/chisel3/ModuleAspect.scala index 3edf0a22..20793cd7 100644 --- a/chiselFrontend/src/main/scala/chisel3/ModuleAspect.scala +++ b/chiselFrontend/src/main/scala/chisel3/ModuleAspect.scala @@ -3,7 +3,6 @@ package chisel3 import chisel3.internal.Builder -import chisel3.experimental.RawModule /** Used by Chisel Aspects to inject Chisel code into modules, after they have been elaborated. * This is an internal API - don't use! diff --git a/chiselFrontend/src/main/scala/chisel3/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/RawModule.scala index 8f201ce6..4155ef4a 100644 --- a/chiselFrontend/src/main/scala/chisel3/RawModule.scala +++ b/chiselFrontend/src/main/scala/chisel3/RawModule.scala @@ -1,12 +1,12 @@ // See LICENSE for license details. -package chisel3.experimental +package chisel3 import scala.collection.mutable.{ArrayBuffer, HashMap} import scala.collection.JavaConversions._ import scala.language.experimental.macros -import chisel3._ +import chisel3.experimental.BaseModule import chisel3.internal._ import chisel3.internal.Builder._ import chisel3.internal.firrtl._ @@ -162,68 +162,71 @@ abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions) } } -/** Legacy Module class that restricts IOs to just io, clock, and reset, and provides a constructor - * for threading through explicit clock and reset. - * - * While this class isn't planned to be removed anytime soon (there are benefits to restricting - * IO), the clock and reset constructors will be phased out. Recommendation is to wrap the module - * in a withClock/withReset/withClockAndReset block, or directly hook up clock or reset IO pins. - */ -abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) +package internal { + + /** Legacy Module class that restricts IOs to just io, clock, and reset, and provides a constructor + * for threading through explicit clock and reset. + * + * While this class isn't planned to be removed anytime soon (there are benefits to restricting + * IO), the clock and reset constructors will be phased out. Recommendation is to wrap the module + * in a withClock/withReset/withClockAndReset block, or directly hook up clock or reset IO pins. + */ + abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) extends MultiIOModule { - // These are to be phased out - protected var override_clock: Option[Clock] = None - protected var override_reset: Option[Bool] = None + // These are to be phased out + protected var override_clock: Option[Clock] = None + protected var override_reset: Option[Bool] = None - // IO for this Module. At the Scala level (pre-FIRRTL transformations), - // connections in and out of a Module may only go through `io` elements. - def io: Record + // IO for this Module. At the Scala level (pre-FIRRTL transformations), + // connections in and out of a Module may only go through `io` elements. + def io: Record - // Allow access to bindings from the compatibility package - protected def _compatIoPortBound() = portsContains(io)// scalastyle:ignore method.name + // Allow access to bindings from the compatibility package + protected def _compatIoPortBound() = portsContains(io)// scalastyle:ignore method.name - protected override def nameIds(rootClass: Class[_]): HashMap[HasId, String] = { - val names = super.nameIds(rootClass) + protected override def nameIds(rootClass: Class[_]): HashMap[HasId, String] = { + val names = super.nameIds(rootClass) - // Allow IO naming without reflection - names.put(io, "io") - names.put(clock, "clock") - names.put(reset, "reset") + // Allow IO naming without reflection + names.put(io, "io") + names.put(clock, "clock") + names.put(reset, "reset") - names - } + names + } - private[chisel3] override def namePorts(names: HashMap[HasId, String]): Unit = { - for (port <- getModulePorts) { - // This should already have been caught - if (!names.contains(port)) throwException(s"Unable to name port $port in $this") - val name = names(port) - port.setRef(ModuleIO(this, _namespace.name(name))) + private[chisel3] override def namePorts(names: HashMap[HasId, String]): Unit = { + for (port <- getModulePorts) { + // This should already have been caught + if (!names.contains(port)) throwException(s"Unable to name port $port in $this") + val name = names(port) + port.setRef(ModuleIO(this, _namespace.name(name))) + } } - } - private[chisel3] override def generateComponent(): Component = { - _compatAutoWrapPorts() // pre-IO(...) compatibility hack + private[chisel3] override def generateComponent(): Component = { + _compatAutoWrapPorts() // pre-IO(...) compatibility hack - // Restrict IO to just io, clock, and reset - require(io != null, "Module must have io") - require(portsContains(io), "Module must have io wrapped in IO(...)") - require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") // scalastyle:ignore line.size.limit - require(portsSize == 3, "Module must only have io, clock, and reset as IO") + // Restrict IO to just io, clock, and reset + require(io != null, "Module must have io") + require(portsContains(io), "Module must have io wrapped in IO(...)") + require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") // scalastyle:ignore line.size.limit + require(portsSize == 3, "Module must only have io, clock, and reset as IO") - super.generateComponent() - } + super.generateComponent() + } - private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { - // Don't generate source info referencing parents inside a module, since this interferes with - // module de-duplication in FIRRTL emission. - implicit val sourceInfo = UnlocatableSourceInfo + private[chisel3] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { + // Don't generate source info referencing parents inside a module, since this interferes with + // module de-duplication in FIRRTL emission. + implicit val sourceInfo = UnlocatableSourceInfo - if (!parentCompileOptions.explicitInvalidate) { - pushCommand(DefInvalid(sourceInfo, io.ref)) - } + if (!parentCompileOptions.explicitInvalidate) { + pushCommand(DefInvalid(sourceInfo, io.ref)) + } - clock := override_clock.getOrElse(Builder.forcedClock) - reset := override_reset.getOrElse(Builder.forcedReset) + clock := override_clock.getOrElse(Builder.forcedClock) + reset := override_reset.getOrElse(Builder.forcedReset) + } } } diff --git a/chiselFrontend/src/main/scala/chisel3/aop/Aspect.scala b/chiselFrontend/src/main/scala/chisel3/aop/Aspect.scala index 86f5b347..9f10a0dd 100644 --- a/chiselFrontend/src/main/scala/chisel3/aop/Aspect.scala +++ b/chiselFrontend/src/main/scala/chisel3/aop/Aspect.scala @@ -2,7 +2,7 @@ package chisel3.aop -import chisel3.experimental.RawModule +import chisel3.RawModule import firrtl.annotations.{Annotation, NoTargetAnnotation} import firrtl.options.Unserializable import firrtl.AnnotationSeq diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala index 13a89971..2c60ce85 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/package.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala @@ -62,17 +62,17 @@ package object core { // These provide temporary compatibility for those who foolishly imported from chisel3.core @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " + - " Use chisel3.experimental.RawModule instead. This alias will be removed in 3.3.", "since the beginning of time") - type RawModule = chisel3.experimental.RawModule + " Use chisel3.RawModule instead. This alias will be removed in 3.3.", "since the beginning of time") + type RawModule = chisel3.RawModule @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " + - "Use chisel3.experimental.MultiIOModule instead. This alias will be removed in 3.3.", "since the beginning of time") - type MultiIOModule = chisel3.experimental.MultiIOModule + "Use chisel3.MultiIOModule instead. This alias will be removed in 3.3.", "since the beginning of time") + type MultiIOModule = chisel3.MultiIOModule @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " + - " Use chisel3.experimental.RawModule instead. This alias will be removed in 3.3.", "since the beginning of time") - type UserModule = chisel3.experimental.RawModule + " Use chisel3.RawModule instead. This alias will be removed in 3.3.", "since the beginning of time") + type UserModule = chisel3.RawModule @deprecated("Avoid importing from chisel3.core, these are not public APIs and may change at any time. " + - "Use chisel3.experimental.MultiIOModule instead. This alias will be removed in 3.3.", "since the beginning of time") - type ImplicitModule = chisel3.experimental.MultiIOModule + "Use chisel3.MultiIOModule instead. This alias will be removed in 3.3.", "since the beginning of time") + type ImplicitModule = chisel3.MultiIOModule @deprecated("Use the version in chisel3._", "3.2") val Bits = chisel3.Bits @@ -213,8 +213,8 @@ package object core { @deprecated("Use the version in chisel3._", "3.2") val withReset = chisel3.withReset - @deprecated("Use the version in chisel3.experimental._", "3.2") - val dontTouch = chisel3.experimental.dontTouch + @deprecated("Use the version in chisel3._", "3.2") + val dontTouch = chisel3.dontTouch @deprecated("Use the version in chisel3.experimental._", "3.2") type BaseModule = chisel3.experimental.BaseModule diff --git a/chiselFrontend/src/main/scala/chisel3/dontTouch.scala b/chiselFrontend/src/main/scala/chisel3/dontTouch.scala new file mode 100644 index 00000000..5dfd9f19 --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/dontTouch.scala @@ -0,0 +1,37 @@ +package chisel3 + +import chisel3.experimental.{ChiselAnnotation, annotate, requireIsHardware} +import firrtl.transforms.DontTouchAnnotation + +/** Marks that a signal should not be removed by Chisel and Firrtl optimization passes + * + * @example {{{ + * class MyModule extends Module { + * val io = IO(new Bundle { + * val a = Input(UInt(32.W)) + * val b = Output(UInt(32.W)) + * }) + * io.b := io.a + * val dead = io.a +% 1.U // normally dead would be pruned by DCE + * dontTouch(dead) // Marking it as such will preserve it + * } + * }}} + * @note Calling this on [[Data]] creates an annotation that Chisel emits to a separate annotations + * file. This file must be passed to FIRRTL independently of the `.fir` file. The execute methods + * in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically. + */ +object dontTouch { // scalastyle:ignore object.name + /** Marks a signal to be preserved in Chisel and Firrtl + * + * @note Requires the argument to be bound to hardware + * @param data The signal to be marked + * @return Unmodified signal `data` + */ + def apply[T <: Data](data: T)(implicit compileOptions: CompileOptions): T = { + if (compileOptions.checkSynthesizable) { + requireIsHardware(data, "Data marked dontTouch") + } + annotate(new ChiselAnnotation { def toFirrtl = DontTouchAnnotation(data.toNamed) }) + data + } +} diff --git a/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala b/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala index 1f7150c8..2a4aa5f5 100644 --- a/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala +++ b/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala @@ -5,7 +5,7 @@ package chisel3.experimental import chisel3.internal.firrtl.Width import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal._ -import chisel3.{ActualDirection, Bits, CompileOptions, Data, Element, PString, Printable, SpecifiedDirection, UInt} +import chisel3.{ActualDirection, Bits, CompileOptions, Data, Element, PString, Printable, RawModule, SpecifiedDirection, UInt} import scala.collection.mutable diff --git a/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala index f49deff4..6b4c1070 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/BiConnect.scala @@ -3,7 +3,7 @@ package chisel3.internal import chisel3._ -import chisel3.experimental.{Analog, BaseModule, RawModule, attach} +import chisel3.experimental.{Analog, BaseModule, attach} import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{Connect, DefInvalid} import scala.language.experimental.macros diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Binding.scala b/chiselFrontend/src/main/scala/chisel3/internal/Binding.scala index 23e35f5c..07c44f9f 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Binding.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Binding.scala @@ -3,7 +3,7 @@ package chisel3.internal import chisel3._ -import chisel3.experimental.{BaseModule, RawModule} +import chisel3.experimental.BaseModule import chisel3.internal.firrtl.LitArg /** Requires that a node is hardware ("bound") diff --git a/chiselFrontend/src/main/scala/chisel3/internal/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/internal/MonoConnect.scala index ace7be20..1c001183 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/MonoConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/MonoConnect.scala @@ -3,7 +3,7 @@ package chisel3.internal import chisel3._ -import chisel3.experimental.{Analog, BaseModule, EnumType, FixedPoint, RawModule, UnsafeEnum} +import chisel3.experimental.{Analog, BaseModule, EnumType, FixedPoint, UnsafeEnum} import chisel3.internal.Builder.pushCommand import chisel3.internal.firrtl.{Connect, DefInvalid} import scala.language.experimental.macros diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index e4b660dd..4643f66c 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -5,7 +5,7 @@ package chisel3.internal.firrtl import chisel3._ import chisel3.internal._ import chisel3.internal.sourceinfo.SourceInfo -import chisel3.experimental.{BaseModule, ChiselAnnotation, Param, RawModule} +import chisel3.experimental.{BaseModule, ChiselAnnotation, Param} // scalastyle:off number.of.types diff --git a/chiselFrontend/src/main/scala/chisel3/package.scala b/chiselFrontend/src/main/scala/chisel3/package.scala index 4a240a8c..51bcf1fe 100644 --- a/chiselFrontend/src/main/scala/chisel3/package.scala +++ b/chiselFrontend/src/main/scala/chisel3/package.scala @@ -142,7 +142,7 @@ package object chisel3 { // scalastyle:ignore package.object.name type InstanceId = internal.InstanceId - type Module = chisel3.experimental.LegacyModule + type Module = chisel3.internal.LegacyModule /** Implicit for custom Printable string interpolator */ implicit class PrintableHelper(val sc: StringContext) extends AnyVal { diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index 158ba65a..1caccfc4 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -3,7 +3,6 @@ package chisel3 import chisel3.internal.ErrorLog -import chisel3.experimental.RawModule import internal.firrtl._ import firrtl._ import firrtl.options.{Phase, PhaseManager, StageError} diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala index 74cd62f3..00a17d86 100644 --- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala +++ b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala @@ -2,9 +2,8 @@ package chisel3.aop.injecting -import chisel3.{Module, ModuleAspect, experimental, withClockAndReset} +import chisel3.{Module, ModuleAspect, experimental, withClockAndReset, RawModule, MultiIOModule} import chisel3.aop._ -import chisel3.experimental.RawModule import chisel3.internal.Builder import chisel3.internal.firrtl.DefModule import chisel3.stage.DesignAnnotation @@ -36,7 +35,7 @@ case class InjectingAspect[T <: RawModule, RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module => val (chiselIR, _) = Builder.build(Module(new ModuleAspect(module) { module match { - case x: experimental.MultiIOModule => withClockAndReset(x.clock, x.reset) { injection(module) } + case x: MultiIOModule => withClockAndReset(x.clock, x.reset) { injection(module) } case x: RawModule => injection(module) } })) diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 24556461..02dfa329 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -300,7 +300,7 @@ package object Chisel { // scalastyle:ignore package.object.name number.of.t import chisel3.CompileOptions abstract class CompatibilityModule(implicit moduleCompileOptions: CompileOptions) - extends chisel3.experimental.LegacyModule { + extends chisel3.internal.LegacyModule { // This class auto-wraps the Module IO with IO(...), allowing legacy code (where IO(...) wasn't // required) to build. // Also provides the clock / reset constructors, which were used before withClock happened. diff --git a/src/main/scala/chisel3/stage/ChiselAnnotations.scala b/src/main/scala/chisel3/stage/ChiselAnnotations.scala index e722bac2..bfce0e8d 100644 --- a/src/main/scala/chisel3/stage/ChiselAnnotations.scala +++ b/src/main/scala/chisel3/stage/ChiselAnnotations.scala @@ -5,7 +5,7 @@ package chisel3.stage import firrtl.annotations.{Annotation, NoTargetAnnotation} import firrtl.options.{HasShellOptions, OptionsException, ShellOption, Unserializable} import chisel3.{ChiselException, Module} -import chisel3.experimental.RawModule +import chisel3.RawModule import chisel3.internal.Builder import chisel3.internal.firrtl.Circuit import firrtl.AnnotationSeq diff --git a/src/main/scala/chisel3/stage/phases/AspectPhase.scala b/src/main/scala/chisel3/stage/phases/AspectPhase.scala index f8038a2c..8d48e338 100644 --- a/src/main/scala/chisel3/stage/phases/AspectPhase.scala +++ b/src/main/scala/chisel3/stage/phases/AspectPhase.scala @@ -3,7 +3,7 @@ package chisel3.stage.phases import chisel3.aop.Aspect -import chisel3.experimental.RawModule +import chisel3.RawModule import chisel3.stage.DesignAnnotation import firrtl.AnnotationSeq import firrtl.options.Phase diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 36892c11..15b4ab1d 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -6,7 +6,7 @@ package chisel3.util import chisel3._ -import chisel3.experimental.{DataMirror, Direction, MultiIOModule, requireIsChiselType} +import chisel3.experimental.{DataMirror, Direction, requireIsChiselType} import chisel3.internal.naming._ // can't use chisel3_ version because of compile order /** An I/O Bundle containing 'valid' and 'ready' signals that handshake diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala index c78c8c0e..d81ed009 100644 --- a/src/test/scala/chiselTests/AnalogSpec.scala +++ b/src/test/scala/chiselTests/AnalogSpec.scala @@ -5,7 +5,7 @@ package chiselTests import chisel3._ import chisel3.util._ import chisel3.testers.BasicTester -import chisel3.experimental.{Analog, attach, BaseModule, RawModule} +import chisel3.experimental.{Analog, attach, BaseModule} // IO for Modules that just connect bus to out class AnalogReaderIO extends Bundle { diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala index 70bd0166..856f6b91 100644 --- a/src/test/scala/chiselTests/BoringUtilsSpec.scala +++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala @@ -5,7 +5,7 @@ package chiselTests import chisel3._ import chisel3.util.Counter import chisel3.testers.BasicTester -import chisel3.experimental.{BaseModule, ChiselAnnotation, MultiIOModule, RawModule, RunFirrtlTransform} +import chisel3.experimental.{BaseModule, ChiselAnnotation, RunFirrtlTransform} import chisel3.util.experimental.BoringUtils import firrtl.{CircuitForm, CircuitState, ChirrtlForm, Transform} diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala index aa1dbc0f..ec0bad66 100644 --- a/src/test/scala/chiselTests/BundleLiteralSpec.scala +++ b/src/test/scala/chiselTests/BundleLiteralSpec.scala @@ -4,7 +4,6 @@ package chiselTests import chisel3._ import chisel3.testers.BasicTester -import chisel3.experimental.RawModule import chisel3.experimental.BundleLiterals._ import chisel3.experimental.BundleLiteralException diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala index d0a1f5c5..9af7e88f 100644 --- a/src/test/scala/chiselTests/ChiselSpec.scala +++ b/src/test/scala/chiselTests/ChiselSpec.scala @@ -6,7 +6,6 @@ import org.scalatest._ import org.scalatest.prop._ import org.scalacheck._ import chisel3._ -import chisel3.experimental.RawModule import chisel3.testers._ import firrtl.options.OptionsException import firrtl.{AnnotationSeq, CommonOptions, ExecutionOptionsManager, FirrtlExecutionFailure, FirrtlExecutionSuccess, HasFirrtlOptions} diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala index f508bb81..58a491ef 100644 --- a/src/test/scala/chiselTests/Clock.scala +++ b/src/test/scala/chiselTests/Clock.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.experimental.RawModule import chisel3.testers.BasicTester class ClockAsUIntTester extends BasicTester { diff --git a/src/test/scala/chiselTests/CloneModuleSpec.scala b/src/test/scala/chiselTests/CloneModuleSpec.scala index ca8bd007..b3bc2b16 100644 --- a/src/test/scala/chiselTests/CloneModuleSpec.scala +++ b/src/test/scala/chiselTests/CloneModuleSpec.scala @@ -4,7 +4,7 @@ package chiselTests import chisel3._ import chisel3.util.{Queue, EnqIO, DeqIO, QueueIO, log2Ceil} -import chisel3.experimental.{CloneModuleAsRecord, IO, MultiIOModule} +import chisel3.experimental.{CloneModuleAsRecord, IO} import chisel3.testers.BasicTester class MultiIOQueue[T <: Data](gen: T, val entries: Int) extends MultiIOModule { diff --git a/src/test/scala/chiselTests/DataPrint.scala b/src/test/scala/chiselTests/DataPrint.scala index 57e44c36..493d3c7a 100644 --- a/src/test/scala/chiselTests/DataPrint.scala +++ b/src/test/scala/chiselTests/DataPrint.scala @@ -5,7 +5,7 @@ package chiselTests import org.scalatest._ import chisel3._ -import chisel3.experimental.{ChiselEnum, FixedPoint, RawModule, MultiIOModule} +import chisel3.experimental.{ChiselEnum, FixedPoint} import chisel3.experimental.BundleLiterals._ class DataPrintSpec extends ChiselFlatSpec with Matchers { diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala index 4c5e819d..1e536a5a 100644 --- a/src/test/scala/chiselTests/Direction.scala +++ b/src/test/scala/chiselTests/Direction.scala @@ -4,7 +4,6 @@ package chiselTests import org.scalatest._ import chisel3._ -import chisel3.experimental.RawModule class DirectionedBundle extends Bundle { val in = Input(UInt(32.W)) @@ -127,7 +126,7 @@ class DirectionSpec extends ChiselPropSpec with Matchers { } } - import chisel3.experimental.{MultiIOModule, DataMirror, Direction, RawModule} + import chisel3.experimental.{DataMirror, Direction} property("Directions should be preserved through cloning and binding of Bundles") { elaborate(new MultiIOModule { diff --git a/src/test/scala/chiselTests/DontTouchSpec.scala b/src/test/scala/chiselTests/DontTouchSpec.scala index 4b1bce8e..ead4ffc9 100644 --- a/src/test/scala/chiselTests/DontTouchSpec.scala +++ b/src/test/scala/chiselTests/DontTouchSpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.experimental.dontTouch class HasDeadCodeChild(withDontTouch: Boolean) extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala index 75ab93ae..7190261c 100644 --- a/src/test/scala/chiselTests/DriverSpec.scala +++ b/src/test/scala/chiselTests/DriverSpec.scala @@ -17,7 +17,7 @@ class DummyModule extends Module { io.out := io.in } -class TypeErrorModule extends chisel3.experimental.MultiIOModule { +class TypeErrorModule extends chisel3.MultiIOModule { val in = IO(Input(UInt(1.W))) val out = IO(Output(SInt(1.W))) out := in diff --git a/src/test/scala/chiselTests/LiteralExtractorSpec.scala b/src/test/scala/chiselTests/LiteralExtractorSpec.scala index 533de888..b56672af 100644 --- a/src/test/scala/chiselTests/LiteralExtractorSpec.scala +++ b/src/test/scala/chiselTests/LiteralExtractorSpec.scala @@ -3,7 +3,7 @@ package chiselTests import chisel3._ -import chisel3.experimental.{FixedPoint, RawModule} +import chisel3.experimental.FixedPoint import chisel3.experimental.BundleLiterals._ import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index ed624f0c..f730d08b 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -142,7 +142,7 @@ class ModuleSpec extends ChiselPropSpec { property("DataMirror.modulePorts should work") { elaborate(new Module { val io = IO(new Bundle { }) - val m = Module(new chisel3.experimental.MultiIOModule { + val m = Module(new chisel3.MultiIOModule { val a = IO(UInt(8.W)) val b = IO(Bool()) }) diff --git a/src/test/scala/chiselTests/MultiIOModule.scala b/src/test/scala/chiselTests/MultiIOModule.scala index 7978970a..e15acc31 100644 --- a/src/test/scala/chiselTests/MultiIOModule.scala +++ b/src/test/scala/chiselTests/MultiIOModule.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.experimental.MultiIOModule import chisel3.testers.BasicTester class MultiIOPlusOne extends MultiIOModule { diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala index 82a5c109..4576176a 100644 --- a/src/test/scala/chiselTests/NamingAnnotationTest.scala +++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala @@ -3,7 +3,7 @@ package chiselTests import chisel3._ -import chisel3.experimental.{MultiIOModule, chiselName} +import chisel3.experimental.chiselName import chisel3.internal.InstanceId import scala.collection.mutable.ListBuffer diff --git a/src/test/scala/chiselTests/RawModuleSpec.scala b/src/test/scala/chiselTests/RawModuleSpec.scala index 88b53457..45d6b58a 100644 --- a/src/test/scala/chiselTests/RawModuleSpec.scala +++ b/src/test/scala/chiselTests/RawModuleSpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.experimental.RawModule import chisel3.testers.BasicTester class UnclockedPlusOne extends RawModule { diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala index 297c5516..2381aadc 100644 --- a/src/test/scala/chiselTests/ResetSpec.scala +++ b/src/test/scala/chiselTests/ResetSpec.scala @@ -3,7 +3,6 @@ package chiselTests import chisel3._ -import chisel3.experimental.{IO, RawModule} import chisel3.util.{Counter, Queue} import chisel3.testers.BasicTester diff --git a/src/test/scala/chiselTests/TransitNameSpec.scala b/src/test/scala/chiselTests/TransitNameSpec.scala index 857d6470..7c5f0578 100644 --- a/src/test/scala/chiselTests/TransitNameSpec.scala +++ b/src/test/scala/chiselTests/TransitNameSpec.scala @@ -4,7 +4,6 @@ package chiselTests import org.scalatest.{FlatSpec, Matchers} import chisel3._ -import chisel3.experimental.RawModule import chisel3.util.TransitName import firrtl.FirrtlExecutionSuccess diff --git a/src/test/scala/chiselTests/Util.scala b/src/test/scala/chiselTests/Util.scala index 82ae7072..f71cd7f3 100644 --- a/src/test/scala/chiselTests/Util.scala +++ b/src/test/scala/chiselTests/Util.scala @@ -5,7 +5,6 @@ package chiselTests import chisel3._ -import chisel3.experimental._ class PassthroughModuleIO extends Bundle { val in = Input(UInt(32.W)) diff --git a/src/test/scala/chiselTests/aop/SelectSpec.scala b/src/test/scala/chiselTests/aop/SelectSpec.scala index d3f72551..f3c756ab 100644 --- a/src/test/scala/chiselTests/aop/SelectSpec.scala +++ b/src/test/scala/chiselTests/aop/SelectSpec.scala @@ -7,7 +7,6 @@ import chiselTests.ChiselFlatSpec import chisel3._ import chisel3.aop.Select.{PredicatedConnect, When, WhenNot} import chisel3.aop.{Aspect, Select} -import chisel3.experimental.RawModule import firrtl.{AnnotationSeq} import scala.reflect.runtime.universe.TypeTag diff --git a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala index d17bfd32..09e401f2 100644 --- a/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala +++ b/src/test/scala/chiselTests/experimental/ProgrammaticPortsSpec.scala @@ -4,7 +4,6 @@ package chiselTests package experimental import chisel3._ -import chisel3.experimental.MultiIOModule // NOTE This is currently an experimental API and subject to change // Example using a private port diff --git a/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala b/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala index 63b1001f..dd0dd09a 100644 --- a/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala +++ b/src/test/scala/chiselTests/stage/ChiselAnnotationsSpec.scala @@ -5,7 +5,6 @@ package chiselTests.stage import org.scalatest.{FlatSpec, Matchers} import chisel3._ import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, DesignAnnotation} -import chisel3.experimental.RawModule import firrtl.options.OptionsException class ChiselAnnotationsSpecFoo extends RawModule { diff --git a/src/test/scala/chiselTests/stage/ChiselMainSpec.scala b/src/test/scala/chiselTests/stage/ChiselMainSpec.scala index 27a3093c..7862acd6 100644 --- a/src/test/scala/chiselTests/stage/ChiselMainSpec.scala +++ b/src/test/scala/chiselTests/stage/ChiselMainSpec.scala @@ -3,10 +3,7 @@ package chiselTests.stage import chisel3._ -import chisel3.stage.{ChiselGeneratorAnnotation, ChiselMain} -import chisel3.experimental.RawModule - -import firrtl.AnnotationSeq +import chisel3.stage.ChiselMain import java.io.File diff --git a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala index f5fe0440..734f571a 100644 --- a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala +++ b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputAnnotationFileSpec.scala @@ -4,7 +4,7 @@ package chiselTests.stage.phases import org.scalatest.{FlatSpec, Matchers} -import chisel3.experimental.RawModule +import chisel3.RawModule import chisel3.stage.ChiselGeneratorAnnotation import chisel3.stage.phases.{AddImplicitOutputAnnotationFile, Elaborate} diff --git a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala index 411aa6ba..1a667365 100644 --- a/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala +++ b/src/test/scala/chiselTests/stage/phases/AddImplicitOutputFileSpec.scala @@ -4,7 +4,7 @@ package chiselTests.stage.phases import org.scalatest.{FlatSpec, Matchers} -import chisel3.experimental.RawModule +import chisel3.RawModule import chisel3.stage.{ChiselGeneratorAnnotation, ChiselOutputFileAnnotation} import chisel3.stage.phases.{AddImplicitOutputFile, Elaborate} diff --git a/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala b/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala index 30fad4f5..1eefcdb6 100644 --- a/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala +++ b/src/test/scala/chiselTests/stage/phases/ConvertSpec.scala @@ -5,7 +5,7 @@ package chiselTests.stage.phases import org.scalatest.{FlatSpec, Matchers} import chisel3._ -import chisel3.experimental.{ChiselAnnotation, RawModule, RunFirrtlTransform} +import chisel3.experimental.{ChiselAnnotation, RunFirrtlTransform} import chisel3.stage.ChiselGeneratorAnnotation import chisel3.stage.phases.{Convert, Elaborate} diff --git a/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala b/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala index 63498adb..a421e9cc 100644 --- a/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala +++ b/src/test/scala/chiselTests/stage/phases/EmitterSpec.scala @@ -4,7 +4,7 @@ package chiselTests.stage.phases import org.scalatest.{FlatSpec, Matchers} -import chisel3.experimental.RawModule +import chisel3.RawModule import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, ChiselOutputFileAnnotation} import chisel3.stage.phases.{Convert, Elaborate, Emitter} |