1 files changed, 3 insertions, 37 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/Annotation.scala
index ec000d93..e54b1bf9 100644
--- a/chiselFrontend/src/main/scala/chisel3/Annotation.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Annotation.scala
@@ -3,7 +3,7 @@
 package chisel3.experimental
 
 import scala.language.existentials
-import chisel3.internal.{Builder, InstanceId}
+import chisel3.internal.{Builder, InstanceId, LegacyModule}
 import chisel3.{CompileOptions, Data}
 import firrtl.Transform
 import firrtl.annotations._
@@ -21,7 +21,7 @@ trait ChiselAnnotation {
 
 /** Mixin for [[ChiselAnnotation]] that instantiates an associated FIRRTL Transform when this Annotation is present
   * during a run of
-  * [[Driver$.execute(args:Array[String],dut:()=>chisel3\.experimental\.RawModule)* Driver.execute]].
+  * [[Driver$.execute(args:Array[String],dut:()=>chisel3\.RawModule)* Driver.execute]].
   * Automatic Transform instantiation is *not* supported when the Circuit and Annotations are serialized before invoking
   * FIRRTL.
   */
@@ -45,40 +45,6 @@ object annotate { // scalastyle:ignore object.name
   }
 }
 
-/** Marks that a signal should not be removed by Chisel and Firrtl optimization passes
-  *
-  * @example {{{
-  * class MyModule extends Module {
-  *   val io = IO(new Bundle {
-  *     val a = Input(UInt(32.W))
-  *     val b = Output(UInt(32.W))
-  *   })
-  *   io.b := io.a
-  *   val dead = io.a +% 1.U // normally dead would be pruned by DCE
-  *   dontTouch(dead) // Marking it as such will preserve it
-  * }
-  * }}}
-  *
-  * @note Calling this on [[Data]] creates an annotation that Chisel emits to a separate annotations
-  * file. This file must be passed to FIRRTL independently of the `.fir` file. The execute methods
-  * in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically.
-  */
-object dontTouch { // scalastyle:ignore object.name
-  /** Marks a signal to be preserved in Chisel and Firrtl
-    *
-    * @note Requires the argument to be bound to hardware
-    * @param data The signal to be marked
-    * @return Unmodified signal `data`
-    */
-  def apply[T <: Data](data: T)(implicit compileOptions: CompileOptions): T = {
-    if (compileOptions.checkSynthesizable) {
-      requireIsHardware(data, "Data marked dontTouch")
-    }
-    annotate(new ChiselAnnotation { def toFirrtl = DontTouchAnnotation(data.toNamed) })
-    data
-  }
-}
-
 /** Marks that a module to be ignored in Dedup Transform in Firrtl pass
   *
   * @example {{{
@@ -119,7 +85,7 @@ object dontTouch { // scalastyle:ignore object.name
 object doNotDedup { // scalastyle:ignore object.name
   /** Marks a module to be ignored in Dedup Transform in Firrtl
     *
-    * @param data The module to be marked
+    * @param module The module to be marked
     * @return Unmodified signal `module`
     */
    def apply[T <: LegacyModule](module: T)(implicit compileOptions: CompileOptions): Unit = {