diff options
| author | Jim Lawson | 2019-03-18 12:17:33 -0700 |
|---|---|---|
| committer | GitHub | 2019-03-18 12:17:33 -0700 |
| commit | 2c449c5d6e23dcbb60e8c64cab6b6f4ba6ae313f (patch) | |
| tree | 3daffa8eb0f57faf31d3977700be38f5be31e59a /chiselFrontend/src/main/scala/chisel3/internal | |
| parent | cfb2f08db9d9df121a82f138dd71297dbcea66cc (diff) | |
Split #974 into two PRs - scalastyle updates (#1037)
* Update style warnings now that subprojects are aggregated.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml
* Remove bogus tests that crept in with git add
* Add missing import.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
3 files changed, 14 insertions, 6 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index f0bb5605..dcf5dbde 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -146,8 +146,11 @@ private[chisel3] trait HasId extends InstanceId { private[chisel3] def getPublicFields(rootClass: Class[_]): Seq[java.lang.reflect.Method] = { // Suggest names to nodes using runtime reflection def getValNames(c: Class[_]): Set[String] = { - if (c == rootClass) Set() - else getValNames(c.getSuperclass) ++ c.getDeclaredFields.map(_.getName) + if (c == rootClass) { + Set() + } else { + getValNames(c.getSuperclass) ++ c.getDeclaredFields.map(_.getName) + } } val valNames = getValNames(this.getClass) def isPublicVal(m: java.lang.reflect.Method) = @@ -225,7 +228,7 @@ private[chisel3] object Builder { def forcedUserModule: RawModule = currentModule match { case Some(module: RawModule) => module case _ => throwException( - "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." + "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." // scalastyle:ignore line.size.limit // A bare api call is, e.g. calling Wire() from the scala console). ) } @@ -346,5 +349,5 @@ private[chisel3] object Builder { * objects. */ object DynamicNamingStack { - def apply() = Builder.namingStack + def apply(): internal.naming.NamingStack = Builder.namingStack } diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala index 07f4db73..59f32542 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala @@ -34,7 +34,7 @@ class ChiselException(message: String, cause: Throwable = null) extends Exceptio sw.write(toString + "\n") sw.write("\t...\n") trimmed.foreach(ste => sw.write(s"\tat $ste\n")) - sw.write("\t... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)\n") + sw.write("\t... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)\n") // scalastyle:ignore line.size.limit sw.toString } } @@ -80,6 +80,7 @@ private[chisel3] class ErrorLog { /** Throw an exception if any errors have yet occurred. */ def checkpoint(): Unit = { + // scalastyle:off line.size.limit regex deprecations.foreach { case ((message, sourceLoc), count) => println(s"${ErrorLog.depTag} $sourceLoc ($count calls): $message") } @@ -112,6 +113,7 @@ private[chisel3] class ErrorLog { // No fatal errors, clear accumulated warnings since they've been reported errors.clear() } + // scalastyle:on line.size.limit regex } /** Returns the best guess at the first stack frame that belongs to user code. diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index c05d402d..0b0d1871 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -7,6 +7,8 @@ import core._ import chisel3.internal._ import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo} +// scalastyle:off number.of.types + case class PrimOp(val name: String) { override def toString: String = name } @@ -77,7 +79,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { protected def minWidth: Int if (forcedWidth) { require(widthArg.get >= minWidth, - s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") + s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") // scalastyle:ignore line.size.limit } } @@ -261,6 +263,7 @@ abstract class Definition extends Command { def id: HasId def name: String = id.getRef.name } +// scalastyle:off line.size.limit case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition |
