diff options
66 files changed, 282 insertions, 211 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index fa23ddaa..65939ef7 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -16,7 +16,7 @@ import chisel3.SourceInfoDoc * of) other Data objects. */ sealed abstract class Aggregate extends Data { - private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { + private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { // scalastyle:ignore cyclomatic.complexity line.size.limit binding = target val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection) @@ -58,7 +58,7 @@ sealed abstract class Aggregate extends Data { } case _ => val childWithDirections = getElements zip getElements.map(_.direction) - throw Binding.MixedDirectionAggregateException(s"Aggregate '$this' can't have elements that are both directioned and undirectioned: $childWithDirections") + throw Binding.MixedDirectionAggregateException(s"Aggregate '$this' can't have elements that are both directioned and undirectioned: $childWithDirections") // scalastyle:ignore line.size.limit } } } @@ -111,17 +111,19 @@ trait VecFactory extends SourceInfoDoc { } /** Truncate an index to implement modulo-power-of-2 addressing. */ - private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { + private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { // scalastyle:ignore line.size.limit + // scalastyle:off if.brace val w = BigInt(n-1).bitLength if (n <= 1) 0.U else if (idx.width.known && idx.width.get <= w) idx else if (idx.width.known) idx(w-1,0) else (idx | 0.U(w.W))(w-1,0) + // scalastyle:on if.brace } } object Vec extends VecFactory - +// scalastyle:off line.size.limit /** A vector (array) of [[Data]] elements. Provides hardware versions of various * collection transformation functions found in software array implementations. * @@ -148,6 +150,7 @@ object Vec extends VecFactory * - when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined) * - Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier */ +// scalastyle:on line.size.limit sealed class Vec[T <: Data] private[core] (gen: => T, val length: Int) extends Aggregate with VecLike[T] { override def toString: String = { @@ -195,7 +198,7 @@ sealed class Vec[T <: Data] private[core] (gen: => T, val length: Int) } // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data - def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this bulkConnect that.asInstanceOf[Data] + def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this bulkConnect that.asInstanceOf[Data] // scalastyle:ignore line.size.limit /** Strong bulk connect, assigning elements in this Vec from elements in a Seq. * @@ -258,9 +261,11 @@ sealed class Vec[T <: Data] private[core] (gen: => T, val length: Int) * Results in "Vec(elt0, elt1, ...)" */ def toPrintable: Printable = { + // scalastyle:off if.brace val elts = if (length == 0) List.empty[Printable] else self flatMap (e => List(e.toPrintable, PString(", "))) dropRight 1 + // scalastyle:on if.brace PString("Vec(") + Printables(elts) + PString(")") } } @@ -332,7 +337,7 @@ object VecInit extends SourceInfoDoc { def tabulate[T <: Data](n: Int)(gen: (Int) => T): Vec[T] = macro VecTransform.tabulate /** @group SourceInfoTransformMacro */ - def do_tabulate[T <: Data](n: Int)(gen: (Int) => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = + def do_tabulate[T <: Data](n: Int)(gen: (Int) => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] = // scalastyle:ignore line.size.limit apply((0 until n).map(i => gen(i))) } @@ -494,11 +499,13 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio // Helper because Bundle elements are reversed before printing private[chisel3] def toPrintableHelper(elts: Seq[(String, Data)]): Printable = { + // scalastyle:off if.brace val xs = if (elts.isEmpty) List.empty[Printable] // special case because of dropRight below else elts flatMap { case (name, data) => List(PString(s"$name -> "), data.toPrintable, PString(", ")) } dropRight 1 // Remove trailing ", " + // scalastyle:on if.brace PString(s"$className(") + Printables(xs) + PString(")") } /** Default "pretty-print" implementation @@ -612,6 +619,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { } } ListMap(nameMap.toSeq sortWith { case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn)) }: _*) + // scalastyle:ignore method.length } /** @@ -638,7 +646,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { private val _containingModule: Option[BaseModule] = Builder.currentModule private val _containingBundles: Seq[Bundle] = Builder.updateBundleStack(this) - override def cloneType : this.type = { + override def cloneType : this.type = { // scalastyle:ignore cyclomatic.complexity method.length // This attempts to infer constructor and arguments to clone this Bundle subtype without // requiring the user explicitly overriding cloneType. import scala.language.existentials @@ -718,7 +726,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { Some(ctor.newInstance().asInstanceOf[this.type]) case (argType :: Nil, Some((_, outerInstance))) => if (outerInstance == null) { - Builder.deprecated(s"chisel3.1 autoclonetype failed, falling back to 3.0 behavior using null as the outer instance." + + Builder.deprecated(s"chisel3.1 autoclonetype failed, falling back to 3.0 behavior using null as the outer instance." + // scalastyle:ignore line.size.limit s" Autoclonetype failure reason: ${outerClassError.get}", Some(s"$clazz")) Some(ctor.newInstance(outerInstance).asInstanceOf[this.type]) @@ -745,7 +753,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { // Get constructor parameters and accessible fields val classSymbol = classSymbolOption.getOrElse(autoClonetypeError(s"scala reflection failed." + " This is known to occur with inner classes on anonymous outer classes." + - " In those cases, autoclonetype only works with no-argument constructors, or you can define a custom cloneType.")) + " In those cases, autoclonetype only works with no-argument constructors, or you can define a custom cloneType.")) // scalastyle:ignore line.size.limit val decls = classSymbol.typeSignature.decls val ctors = decls.collect { case meth: MethodSymbol if meth.isConstructor => meth } @@ -795,8 +803,10 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { val accessorsName = accessors.filter(_.isStable).map(_.name.toString) val paramsDiff = ctorParamsNames.toSet -- accessorsName.toSet if (!paramsDiff.isEmpty) { + // scalastyle:off line.size.limit autoClonetypeError(s"constructor has parameters (${paramsDiff.toList.sorted.mkString(", ")}) that are not both immutable and accessible." + " Either make all parameters immutable and accessible (vals) so cloneType can be inferred, or define a custom cloneType method.") + // scalastyle:on line.size.limit } // Get all the argument values @@ -813,8 +823,10 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { case (paramName, paramVal: Data) if paramVal.topBindingOpt.isDefined => paramName } if (boundDataParamNames.nonEmpty) { + // scalastyle:off line.size.limit autoClonetypeError(s"constructor parameters (${boundDataParamNames.sorted.mkString(", ")}) have values that are hardware types, which is likely to cause subtle errors." + " Use chisel types instead: use the value before it is turned to a hardware type (with Wire(...), Reg(...), etc) or use chiselTypeOf(...) to extract the chisel type.") + // scalastyle:on line.size.limit } // Clone unbound parameters in case they are being used as bundle fields. @@ -833,9 +845,11 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { clone._outerInst = this._outerInst if (!clone.typeEquivalent(this)) { + // scalastyle:off line.size.limit autoClonetypeError(s"Automatically cloned $clone not type-equivalent to base $this." + " Constructor argument values were inferred: ensure that variable names are consistent and have the same value throughout the constructor chain," + " and that the constructor is deterministic.") + // scalastyle:on line.size.limit } clone @@ -848,4 +862,6 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record { * the fields in the order they were defined */ override def toPrintable: Printable = toPrintableHelper(elements.toList.reverse) + // scalastyle:off method.length } +// scalastyle:off file.size.limit diff --git a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala index cfee67cb..93a02139 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala @@ -19,7 +19,7 @@ trait ChiselAnnotation { } object ChiselAnnotation { @deprecated("Write a custom ChiselAnnotation subclass instead", "3.1") - def apply(component: InstanceId, transformClass: Class[_ <: Transform], value: String) = + def apply(component: InstanceId, transformClass: Class[_ <: Transform], value: String): ChiselLegacyAnnotation = ChiselLegacyAnnotation(component, transformClass, value) @deprecated("Write a custom ChiselAnnotation subclass instead", "3.1") def unapply(anno: ChiselAnnotation): Option[(InstanceId, Class[_ <: Transform], String)] = diff --git a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala index 77db3692..054222c3 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala @@ -32,10 +32,10 @@ object assert { // scalastyle:ignore object.name * that */ // Macros currently can't take default arguments, so we need two functions to emulate defaults. - def apply(cond: Bool, message: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = macro apply_impl_msg_data + def apply(cond: Bool, message: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = macro apply_impl_msg_data // scalastyle:ignore line.size.limit def apply(cond: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = macro apply_impl - def apply_impl_msg_data(c: Context)(cond: c.Tree, message: c.Tree, data: c.Tree*)(sourceInfo: c.Tree, compileOptions: c.Tree): c.Tree = { + def apply_impl_msg_data(c: Context)(cond: c.Tree, message: c.Tree, data: c.Tree*)(sourceInfo: c.Tree, compileOptions: c.Tree): c.Tree = { // scalastyle:ignore line.size.limit import c.universe._ val p = c.enclosingPosition val condStr = s"${p.source.file.name}:${p.line} ${p.lineContent.trim}" @@ -51,7 +51,7 @@ object assert { // scalastyle:ignore object.name q"$apply_impl_do($cond, $condStr, _root_.scala.None)($sourceInfo, $compileOptions)" } - def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) { + def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) { // scalastyle:ignore line.size.limit val escLine = line.replaceAll("%", "%%") when (!(cond || Module.reset.asBool)) { val fmt = message match { diff --git a/chiselFrontend/src/main/scala/chisel3/core/Attach.scala b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala index 8cb58f1c..5fb89b18 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Attach.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala @@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.{SourceInfo} object attach { // scalastyle:ignore object.name // Exceptions that can be generated by attach case class AttachException(message: String) extends ChiselException(message) - def ConditionalAttachException = + def ConditionalAttachException: AttachException = // scalastyle:ignore method.name AttachException(": Conditional attach is not allowed!") // Actual implementation diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala index 897ccacf..b1f9bcb5 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala @@ -23,6 +23,7 @@ import chisel3.internal.sourceinfo._ */ object BiConnect { + // scalastyle:off method.name public.methods.have.type // These are all the possible exceptions that can be thrown. case class BiConnectException(message: String) extends ChiselException(message) // These are from element-level connection @@ -47,7 +48,7 @@ object BiConnect { BiConnectException(sourceInfo.makeMessage(": Analog previously bulk connected at " + _)) def DontCareCantBeSink = BiConnectException(": DontCare cannot be a connection sink (LHS)") - + // scalastyle:on method.name public.methods.have.type /** This function is what recursively tries to connect a left and right together * @@ -55,7 +56,7 @@ object BiConnect { * during the recursive decent and then rethrow them with extra information added. * This gives the user a 'path' to where in the connections things went wrong. */ - def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: RawModule): Unit = { + def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: RawModule): Unit = { // scalastyle:ignore line.size.limit cyclomatic.complexity method.length (left, right) match { // Handle element case (root case) case (left_a: Analog, right_a: Analog) => @@ -207,7 +208,7 @@ object BiConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: RawModule): Unit = { + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: RawModule): Unit = { // scalastyle:ignore line.size.limit cyclomatic.complexity method.length import BindingDirection.{Internal, Input, Output} // Using extensively so import these // If left or right have no location, assume in context module // This can occur if one of them is a literal, unbound will error previously diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala index 4c352bc6..55e6bcf9 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + package chisel3.core import chisel3.internal.ChiselException @@ -23,7 +25,7 @@ object Binding { /** Requires that a node is hardware ("bound") */ object requireIsHardware { - def apply(node: Data, msg: String = "") = { + def apply(node: Data, msg: String = ""): Unit = { node._parent match { // Compatibility layer hack case Some(x: BaseModule) => x._compatAutoWrapPorts case _ => @@ -39,7 +41,7 @@ object requireIsHardware { /** Requires that a node is a chisel type (not hardware, "unbound") */ object requireIsChiselType { - def apply(node: Data, msg: String = "") = if (node.topBindingOpt.isDefined) { + def apply(node: Data, msg: String = ""): Unit = if (node.topBindingOpt.isDefined) { val prefix = if (msg.nonEmpty) s"$msg " else "" throw Binding.ExpectedChiselTypeException(s"$prefix'$node' must be a Chisel type, not hardware") } @@ -60,7 +62,7 @@ object BindingDirection { /** Determine the BindingDirection of an Element given its top binding and resolved direction. */ - def from(binding: TopBinding, direction: ActualDirection) = { + def from(binding: TopBinding, direction: ActualDirection): BindingDirection = { binding match { case PortBinding(_) => direction match { case ActualDirection.Output => Output @@ -82,13 +84,13 @@ sealed trait TopBinding extends Binding // Constrained-ness refers to whether 'bound by Module boundaries' // An unconstrained binding, like a literal, can be read by everyone sealed trait UnconstrainedBinding extends TopBinding { - def location = None + def location: Option[BaseModule] = None } // A constrained binding can only be read/written by specific modules // Location will track where this Module is sealed trait ConstrainedBinding extends TopBinding { def enclosure: BaseModule - def location = Some(enclosure) + def location: Option[BaseModule] = Some(enclosure) } // A binding representing a data that cannot be (re)assigned to. @@ -103,7 +105,7 @@ case class RegBinding(enclosure: RawModule) extends ConstrainedBinding case class WireBinding(enclosure: RawModule) extends ConstrainedBinding case class ChildBinding(parent: Data) extends Binding { - def location = parent.topBinding.location + def location: Option[BaseModule] = parent.topBinding.location } // A DontCare element has a specific Binding, somewhat like a literal. // It is a source (RHS). It may only be connected/applied to sinks. diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index db2562a5..7270d92b 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -12,7 +12,7 @@ import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfo UIntTransform} import chisel3.internal.firrtl.PrimOp._ -//scalastyle:off method.name +// scalastyle:off method.name line.size.limit file.size.limit /** Element is a leaf data type: it cannot contain other [[Data]] objects. Example uses are for representing primitive * data types, like integers and bits. @@ -1761,7 +1761,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element { private[core] override def typeEquivalent(that: Data): Boolean = that.isInstanceOf[Analog] && this.width == that.width - override def litOption = None + override def litOption: Option[BigInt] = None def cloneType: this.type = new Analog(width).asInstanceOf[this.type] diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala index 57acd7b3..e8dc2bfe 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala @@ -123,11 +123,11 @@ abstract class ExtModule(val params: Map[String, Param] = Map.empty[String, Para * }}} * @note The parameters API is experimental and may change */ -abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param])(implicit compileOptions: CompileOptions) extends BaseBlackBox { +abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param])(implicit compileOptions: CompileOptions) extends BaseBlackBox { // scalastyle:ignore line.size.limit def io: Record // Allow access to bindings from the compatibility package - protected def _compatIoPortBound() = portsContains(io) + protected def _compatIoPortBound() = portsContains(io) // scalastyle:ignore method.name private[core] override def generateComponent(): Component = { _compatAutoWrapPorts() // pre-IO(...) compatibility hack diff --git a/chiselFrontend/src/main/scala/chisel3/core/Clock.scala b/chiselFrontend/src/main/scala/chisel3/core/Clock.scala index 1bc2260c..364ac5aa 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Clock.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Clock.scala @@ -20,17 +20,17 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element private[core] def typeEquivalent(that: Data): Boolean = this.getClass == that.getClass - override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match { + override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match { // scalastyle:ignore line.size.limit case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions) case _ => super.badConnect(that)(sourceInfo) } - override def litOption = None + override def litOption: Option[BigInt] = None /** Not really supported */ def toPrintable: Printable = PString("CLOCK") - override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) + override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) // scalastyle:ignore line.size.limit private[core] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { this := that diff --git a/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala index e22519d9..a2f94e51 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala @@ -35,21 +35,21 @@ object CompileOptions { object ExplicitCompileOptions { case class CompileOptionsClass ( - // Should Record connections require a strict match of fields. - // If true and the same fields aren't present in both source and sink, a MissingFieldException, - // MissingLeftFieldException, or MissingRightFieldException will be thrown. - val connectFieldsMustMatch: Boolean, - // When creating an object that takes a type argument, the argument must be unbound (a pure type). - val declaredTypeMustBeUnbound: Boolean, - // If a connection operator fails, don't try the connection with the operands (source and sink) reversed. - val dontTryConnectionsSwapped: Boolean, - // If connection directionality is not explicit, do not use heuristics to attempt to determine it. - val dontAssumeDirectionality: Boolean, - // Check that referenced Data have actually been declared. - val checkSynthesizable: Boolean, - // Require an explicit DontCare assignment to generate a firrtl DefInvalid - val explicitInvalidate: Boolean - ) extends CompileOptions + // Should Record connections require a strict match of fields. + // If true and the same fields aren't present in both source and sink, a MissingFieldException, + // MissingLeftFieldException, or MissingRightFieldException will be thrown. + val connectFieldsMustMatch: Boolean, + // When creating an object that takes a type argument, the argument must be unbound (a pure type). + val declaredTypeMustBeUnbound: Boolean, + // If a connection operator fails, don't try the connection with the operands (source and sink) reversed. + val dontTryConnectionsSwapped: Boolean, + // If connection directionality is not explicit, do not use heuristics to attempt to determine it. + val dontAssumeDirectionality: Boolean, + // Check that referenced Data have actually been declared. + val checkSynthesizable: Boolean, + // Require an explicit DontCare assignment to generate a firrtl DefInvalid + val explicitInvalidate: Boolean + ) extends CompileOptions // Collection of "not strict" connection compile options. // These provide compatibility with existing code. diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala index 06fb27cc..45afed94 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala @@ -28,7 +28,7 @@ object SpecifiedDirection { */ case object Flip extends SpecifiedDirection - def flip(dir: SpecifiedDirection) = dir match { + def flip(dir: SpecifiedDirection): SpecifiedDirection = dir match { case Unspecified => Flip case Flip => Unspecified case Output => Input @@ -38,7 +38,7 @@ object SpecifiedDirection { /** Returns the effective SpecifiedDirection of this node given the parent's effective SpecifiedDirection * and the user-specified SpecifiedDirection of this node. */ - def fromParent(parentDirection: SpecifiedDirection, thisDirection: SpecifiedDirection) = + def fromParent(parentDirection: SpecifiedDirection, thisDirection: SpecifiedDirection): SpecifiedDirection = (parentDirection, thisDirection) match { case (SpecifiedDirection.Output, _) => SpecifiedDirection.Output case (SpecifiedDirection.Input, _) => SpecifiedDirection.Input @@ -105,8 +105,8 @@ object DataMirror { } // Internal reflection-style APIs, subject to change and removal whenever. - object internal { - def isSynthesizable(target: Data) = target.topBindingOpt.isDefined + object internal { // scalastyle:ignore object.name + def isSynthesizable(target: Data): Boolean = target.topBindingOpt.isDefined // For those odd cases where you need to care about object reference and uniqueness def chiselTypeClone[T<:Data](target: Data): T = { target.cloneTypeFull.asInstanceOf[T] @@ -222,7 +222,7 @@ object Flipped { * @groupdesc Connect Utilities for connecting hardware components * @define coll data */ -abstract class Data extends HasId with NamedComponent with SourceInfoDoc { +abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // scalastyle:ignore number.of.methods // This is a bad API that punches through object boundaries. @deprecated("pending removal once all instances replaced", "chisel3") private[chisel3] def flatten: IndexedSeq[Element] = { @@ -252,7 +252,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { * the compatibility layer where, at the elements, Flip is Input and unspecified is Output. * DO NOT USE OUTSIDE THIS PURPOSE. THIS OPERATION IS DANGEROUS! */ - private[core] def _assignCompatibilityExplicitDirection: Unit = { + private[core] def _assignCompatibilityExplicitDirection: Unit = { // scalastyle:off method.name (this, _specifiedDirection) match { case (_: Analog, _) => // nothing to do case (_, SpecifiedDirection.Unspecified) => _specifiedDirection = SpecifiedDirection.Output @@ -332,7 +332,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit = throwException(s"cannot connect ${this} and ${that}") - private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { + private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit if (connectCompileOptions.checkSynthesizable) { requireIsHardware(this, "data to be connected") requireIsHardware(that, "data to be connected") @@ -352,7 +352,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { this legacyConnect that } } - private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { + private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit if (connectCompileOptions.checkSynthesizable) { requireIsHardware(this, s"data to be bulk-connected") requireIsHardware(that, s"data to be bulk-connected") @@ -384,7 +384,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { private[chisel3] def lref: Node = { requireIsHardware(this) topBindingOpt match { - case Some(binding: ReadOnlyBinding) => throwException(s"internal error: attempted to generate LHS ref to ReadOnlyBinding $binding") + case Some(binding: ReadOnlyBinding) => throwException(s"internal error: attempted to generate LHS ref to ReadOnlyBinding $binding") // scalastyle:ignore line.size.limit case Some(binding: TopBinding) => Node(this) case opt => throwException(s"internal error: unknown binding $opt in generating LHS ref") } @@ -432,7 +432,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { * @param that the $coll to connect to * @group Connect */ - final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions) + final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions) // scalastyle:ignore line.size.limit /** Connect this $coll to that $coll bi-directionally and element-wise. * @@ -441,7 +441,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { * @param that the $coll to connect to * @group Connect */ - final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions) + final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions) // scalastyle:ignore line.size.limit @chiselRuntimeDeprecated @deprecated("litArg is deprecated, use litOption or litTo*Option", "chisel3.2") @@ -626,7 +626,7 @@ object Wire extends WireFactory */ object WireDefault { - private def applyImpl[T <: Data](t: T, init: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + private def applyImpl[T <: Data](t: T, init: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { // scalastyle:ignore line.size.limit implicit val noSourceInfo = UnlocatableSourceInfo val x = Wire(t) requireIsHardware(init, "wire initializer") @@ -641,7 +641,7 @@ object WireDefault { * @note This is really just a specialized form of `apply[T <: Data](t: T, init: T): T` with [[DontCare]] * as `init` */ - def apply[T <: Data](t: T, init: DontCare.type)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { + def apply[T <: Data](t: T, init: DontCare.type)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { // scalastyle:ignore line.size.limit applyImpl(t, init) } @@ -678,19 +678,19 @@ object DontCare extends Element { private[chisel3] override val width: Width = UnknownWidth() bind(DontCareBinding(), SpecifiedDirection.Output) - override def cloneType = DontCare + override def cloneType: this.type = DontCare override def toString: String = "DontCare()" - override def litOption = None + override def litOption: Option[BigInt] = None def toPrintable: Printable = PString("DONTCARE") - private[core] def connectFromBits(that: chisel3.core.Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { + private[core] def connectFromBits(that: chisel3.core.Bits)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit Builder.error("connectFromBits: DontCare cannot be a connection sink (LHS)") } - def do_asUInt(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): chisel3.core.UInt = { + def do_asUInt(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): chisel3.core.UInt = { // scalastyle:ignore line.size.limit Builder.error("DontCare does not have a UInt representation") 0.U } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala index 09e30fec..f9211ee7 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala @@ -11,6 +11,7 @@ import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform, Unlocatable import chisel3.SourceInfoDoc object Mem { + // scalastyle:off line.size.limit @chiselRuntimeDeprecated @deprecated("Mem argument order should be size, t; this will be removed by the official release", "chisel3") def apply[T <: Data](t: T, size: Int)(implicit compileOptions: CompileOptions): Mem[T] = do_apply(size, t)(UnlocatableSourceInfo, compileOptions) diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 751d5401..0a5e522f 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -204,14 +204,14 @@ abstract class BaseModule extends HasId { /** Desired name of this module. Override this to give this module a custom, perhaps parametric, * name. */ - def desiredName = this.getClass.getName.split('.').last + def desiredName:String = this.getClass.getName.split('.').last /** Legalized name of this module. */ final lazy val name = try { Builder.globalNamespace.name(desiredName) } catch { case e: NullPointerException => throwException( - s"Error: desiredName of ${this.getClass.getName} is null. Did you evaluate 'name' before all values needed by desiredName were available?", e) + s"Error: desiredName of ${this.getClass.getName} is null. Did you evaluate 'name' before all values needed by desiredName were available?", e) // scalastyle:ignore line.size.limit case t: Throwable => throw t } @@ -272,7 +272,7 @@ abstract class BaseModule extends HasId { * * TODO: remove this, perhaps by removing Bindings checks in compatibility mode. */ - def _compatAutoWrapPorts() {} + def _compatAutoWrapPorts() {} // scalastyle:ignore method.name // // BaseModule User API functions @@ -285,7 +285,7 @@ abstract class BaseModule extends HasId { /** Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to * io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO. */ - protected def _bindIoInPlace(iodef: Data): Unit = { + protected def _bindIoInPlace(iodef: Data): Unit = { // scalastyle:ignore method.name // Compatibility code: Chisel2 did not require explicit direction on nodes // (unspecified treated as output, and flip on nothing was input). // This sets assigns the explicit directions required by newer semantics on @@ -334,7 +334,7 @@ abstract class BaseModule extends HasId { * TODO(twigg): Specifically walk the Data definition to call out which nodes * are problematic. */ - protected def IO[T<:Data](iodef: T): T = chisel3.core.IO.apply(iodef) + protected def IO[T<:Data](iodef: T): T = chisel3.core.IO.apply(iodef) // scalastyle:ignore method.name // // Internal Functions @@ -344,7 +344,7 @@ abstract class BaseModule extends HasId { private[chisel3] var _component: Option[Component] = None /** Signal name (for simulation). */ - override def instanceName = + override def instanceName: String = if (_parent == None) name else _component match { case None => getRef.name case Some(c) => getRef fullName c diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala index 0773c7a2..6a4ae9bf 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala @@ -33,6 +33,7 @@ import chisel3.internal.sourceinfo.SourceInfo */ object MonoConnect { + // scalastyle:off method.name public.methods.have.type // These are all the possible exceptions that can be thrown. case class MonoConnectException(message: String) extends ChiselException(message) // These are from element-level connection @@ -51,6 +52,7 @@ object MonoConnect { MonoConnectException(s": Sink ($sink) and Source ($source) have different types.") def DontCareCantBeSink = MonoConnectException(": DontCare cannot be a connection sink (LHS)") + // scalastyle:on method.name public.methods.have.type /** This function is what recursively tries to connect a sink and source together * @@ -58,8 +60,7 @@ object MonoConnect { * during the recursive decent and then rethrow them with extra information added. * This gives the user a 'path' to where in the connections things went wrong. */ - //scalastyle:off cyclomatic.complexity method.length - def connect( + def connect( //scalastyle:off cyclomatic.complexity method.length sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Data, @@ -157,7 +158,7 @@ object MonoConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: RawModule): Unit = { + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: RawModule): Unit = { // scalastyle:ignore line.size.limit import BindingDirection.{Internal, Input, Output} // Using extensively so import these // If source has no location, assume in context module // This can occur if is a literal, unbound will error previously @@ -196,7 +197,7 @@ object MonoConnect { throw UnreadableSourceException } } - case (Input, Output) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink) + case (Input, Output) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink) // scalastyle:ignore line.size.limit case (Input, _) => throw UnwritableSinkException } } diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala index 7b3d8d4f..c724f682 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala @@ -54,14 +54,14 @@ sealed abstract class Printable { */ def unpack(ctx: Component): (String, Iterable[String]) /** Allow for appending Printables like Strings */ - final def +(that: Printable) = Printables(List(this, that)) + final def +(that: Printable): Printables = Printables(List(this, that)) /** Allow for appending Strings to Printables */ - final def +(that: String) = Printables(List(this, PString(that))) + final def +(that: String): Printables = Printables(List(this, PString(that))) } object Printable { /** Pack standard printf fmt, args* style into Printable */ - def pack(fmt: String, data: Data*): Printable = { + def pack(fmt: String, data: Data*): Printable = { // scalastyle:ignore method.length val args = data.toIterator // Error handling diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala index 53b62bc8..5c2f89e9 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala @@ -91,10 +91,10 @@ object printf { // scalastyle:ignore object.name } } - private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { + private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit val clock = Builder.forcedClock pushCommand(Printf(sourceInfo, clock.ref, pable)) } - private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = + private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = // scalastyle:ignore line.size.limit printfWithoutReset(Printable.pack(fmt, data:_*)) } diff --git a/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala index 1a9911e6..00e78295 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala @@ -56,7 +56,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) } - private[core] override def generateComponent(): Component = { + private[core] override def generateComponent(): Component = { // scalastyle:ignore cyclomatic.complexity require(!_closed, "Can't generate module more than once") _closed = true @@ -164,22 +164,22 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) @chiselRuntimeDeprecated @deprecated("Module constructor with override _clock deprecated, use withClock", "chisel3") - def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions) + def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions) // scalastyle:ignore line.size.limit @chiselRuntimeDeprecated @deprecated("Module constructor with override _reset deprecated, use withReset", "chisel3") - def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(None, Option(_reset))(moduleCompileOptions) + def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(None, Option(_reset))(moduleCompileOptions) // scalastyle:ignore line.size.limit @chiselRuntimeDeprecated @deprecated("Module constructor with override _clock, _reset deprecated, use withClockAndReset", "chisel3") - def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions) + def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions) // scalastyle:ignore line.size.limit // IO for this Module. At the Scala level (pre-FIRRTL transformations), // connections in and out of a Module may only go through `io` elements. def io: Record // Allow access to bindings from the compatibility package - protected def _compatIoPortBound() = portsContains(io) + protected def _compatIoPortBound() = portsContains(io)// scalastyle:ignore method.name protected override def nameIds(rootClass: Class[_]): HashMap[HasId, String] = { val names = super.nameIds(rootClass) @@ -207,7 +207,7 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) // Restrict IO to just io, clock, and reset require(io != null, "Module must have io") require(portsContains(io), "Module must have io wrapped in IO(...)") - require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") + require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") // scalastyle:ignore line.size.limit require(portsSize == 3, "Module must only have io, clock, and reset as IO") super.generateComponent() diff --git a/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala b/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala index 8feb0541..f9414901 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala @@ -16,11 +16,11 @@ import firrtl.annotations._ object EnumAnnotations { case class EnumComponentAnnotation(target: Named, enumTypeName: String) extends SingleTargetAnnotation[Named] { - def duplicate(n: Named) = this.copy(target = n) + def duplicate(n: Named): EnumComponentAnnotation = this.copy(target = n) } case class EnumComponentChiselAnnotation(target: InstanceId, enumTypeName: String) extends ChiselAnnotation { - def toFirrtl = EnumComponentAnnotation(target.toNamed, enumTypeName) + def toFirrtl: EnumComponentAnnotation = EnumComponentAnnotation(target.toNamed, enumTypeName) } case class EnumDefAnnotation(enumTypeName: String, definition: Map[String, BigInt]) extends NoTargetAnnotation @@ -52,8 +52,9 @@ abstract class EnumType(private val factory: EnumFactory, selfAnnotating: Boolea requireIsHardware(this, "bits operated on") requireIsHardware(other, "bits operated on") - if(!this.typeEquivalent(other)) + if(!this.typeEquivalent(other)) { throwException(s"Enum types are not equivalent: ${this.enumTypeName}, ${other.enumTypeName}") + } pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref)) } @@ -75,12 +76,14 @@ abstract class EnumType(private val factory: EnumFactory, selfAnnotating: Boolea final def > (that: EnumType): Bool = macro SourceInfoTransform.thatArg final def >= (that: EnumType): Bool = macro SourceInfoTransform.thatArg + // scalastyle:off line.size.limit method.name def do_=== (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, EqualOp, that) def do_=/= (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, NotEqualOp, that) def do_< (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, LessOp, that) def do_> (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, GreaterOp, that) def do_<= (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, LessEqOp, that) def do_>= (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, GreaterEqOp, that) + // scalastyle:on line.size.limit method.name override def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(width), AsUIntOp, ref)) @@ -99,10 +102,11 @@ abstract class EnumType(private val factory: EnumFactory, selfAnnotating: Boolea if (litOption.isDefined) { val index = factory.all.indexOf(this) - if (index < factory.all.length-1) - factory.all(index+1).asInstanceOf[this.type] - else + if (index < factory.all.length-1) { + factory.all(index + 1).asInstanceOf[this.type] + } else { factory.all.head.asInstanceOf[this.type] + } } else { val enums_with_nexts = factory.all zip (factory.all.tail :+ factory.all.head) val next_enum = SeqUtils.priorityMux(enums_with_nexts.map { case (e,n) => (this === e, n) } ) @@ -168,8 +172,8 @@ abstract class EnumFactory { enum_records.find(_.inst.litValue() == id).map(_.name) } - protected def Value: Type = macro EnumMacros.ValImpl - protected def Value(id: UInt): Type = macro EnumMacros.ValCustomImpl + protected def Value: Type = macro EnumMacros.ValImpl // scalastyle:off method.name + protected def Value(id: UInt): Type = macro EnumMacros.ValCustomImpl // scalastyle:off method.name protected def do_Value(names: Seq[String]): Type = { val result = new Type @@ -189,10 +193,12 @@ abstract class EnumFactory { protected def do_Value(names: Seq[String], id: UInt): Type = { // TODO: These throw ExceptionInInitializerError which can be confusing to the user. Get rid of the error, and just // throw an exception - if (id.litOption.isEmpty) + if (id.litOption.isEmpty) { throwException(s"$enumTypeName defined with a non-literal type") - if (id.litValue() < this.id) + } + if (id.litValue() < this.id) { throwException(s"Enums must be strictly increasing: $enumTypeName") + } this.id = id.litValue() do_Value(names) @@ -201,6 +207,7 @@ abstract class EnumFactory { def apply(): Type = new Type def apply(n: UInt)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Type = { + // scalastyle:off line.size.limit if (n.litOption.isDefined) { val result = enumInstances.find(_.litValue == n.litValue) @@ -223,17 +230,18 @@ abstract class EnumFactory { result } } + // scalastyle:on line.size.limit } private[core] object EnumMacros { - def ValImpl(c: Context) : c.Tree = { + def ValImpl(c: Context) : c.Tree = { // scalastyle:off method.name import c.universe._ val names = getNames(c) q"""this.do_Value(Seq(..$names))""" } - def ValCustomImpl(c: Context)(id: c.Expr[UInt]) = { + def ValCustomImpl(c: Context)(id: c.Expr[UInt]): c.universe.Tree = { // scalastyle:off method.name import c.universe._ val names = getNames(c) q"""this.do_Value(Seq(..$names), $id)""" @@ -249,8 +257,9 @@ private[core] object EnumMacros { if rhs.pos == c.macroApplication.pos => name.decoded } - if (names.isEmpty) + if (names.isEmpty) { c.abort(c.enclosingPosition, "Value cannot be called without assigning to an enum") + } names } diff --git a/chiselFrontend/src/main/scala/chisel3/core/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala index fb246e1b..78fc0fc5 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/When.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala @@ -28,11 +28,11 @@ object when { // scalastyle:ignore object.name * }}} */ - def apply(cond: => Bool)(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { + def apply(cond: => Bool)(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { // scalastyle:ignore line.size.limit new WhenContext(sourceInfo, Some(() => cond), block) } } - + /** A WhenContext may represent a when, and elsewhen, or an * otherwise. Since FIRRTL does not have an "elsif" statement, * alternatives must be mapped to nested if-else statements inside @@ -51,8 +51,8 @@ final class WhenContext(sourceInfo: SourceInfo, cond: Option[() => Bool], block: * declaration and assignment of the Bool node of the predicate in * the correct place. */ - def elsewhen (elseCond: => Bool)(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { - new WhenContext(sourceInfo, Some(() => elseCond), block, firrtlDepth+1) + def elsewhen (elseCond: => Bool)(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { // scalastyle:ignore line.size.limit + new WhenContext(sourceInfo, Some(() => elseCond), block, firrtlDepth + 1) } /** This block of logic gets executed only if the above conditions @@ -63,10 +63,10 @@ final class WhenContext(sourceInfo: SourceInfo, cond: Option[() => Bool], block: * place. */ def otherwise(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = - new WhenContext(sourceInfo, None, block, firrtlDepth+1) + new WhenContext(sourceInfo, None, block, firrtlDepth + 1) /* - * + * */ if (firrtlDepth > 0) { pushCommand(AltBegin(sourceInfo)) } cond.foreach( c => pushCommand(WhenBegin(sourceInfo, c().ref)) ) diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala index cd75a8a0..46db337b 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/package.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala @@ -26,7 +26,7 @@ package chisel3 { implicit class fromBigIntToLiteral(bigint: BigInt) { /** Int to Bool conversion, allowing compact syntax like 1.B and 0.B */ - def B: Bool = bigint match { + def B: Bool = bigint match { // scalastyle:ignore method.name case bigint if bigint == 0 => Bool.Lit(false) case bigint if bigint == 1 => Bool.Lit(true) case bigint => Builder.error(s"Cannot convert $bigint to Bool, must be 0 or 1"); Bool.Lit(false) diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index f0bb5605..dcf5dbde 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -146,8 +146,11 @@ private[chisel3] trait HasId extends InstanceId { private[chisel3] def getPublicFields(rootClass: Class[_]): Seq[java.lang.reflect.Method] = { // Suggest names to nodes using runtime reflection def getValNames(c: Class[_]): Set[String] = { - if (c == rootClass) Set() - else getValNames(c.getSuperclass) ++ c.getDeclaredFields.map(_.getName) + if (c == rootClass) { + Set() + } else { + getValNames(c.getSuperclass) ++ c.getDeclaredFields.map(_.getName) + } } val valNames = getValNames(this.getClass) def isPublicVal(m: java.lang.reflect.Method) = @@ -225,7 +228,7 @@ private[chisel3] object Builder { def forcedUserModule: RawModule = currentModule match { case Some(module: RawModule) => module case _ => throwException( - "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." + "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." // scalastyle:ignore line.size.limit // A bare api call is, e.g. calling Wire() from the scala console). ) } @@ -346,5 +349,5 @@ private[chisel3] object Builder { * objects. */ object DynamicNamingStack { - def apply() = Builder.namingStack + def apply(): internal.naming.NamingStack = Builder.namingStack } diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala index 07f4db73..59f32542 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala @@ -34,7 +34,7 @@ class ChiselException(message: String, cause: Throwable = null) extends Exceptio sw.write(toString + "\n") sw.write("\t...\n") trimmed.foreach(ste => sw.write(s"\tat $ste\n")) - sw.write("\t... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)\n") + sw.write("\t... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)\n") // scalastyle:ignore line.size.limit sw.toString } } @@ -80,6 +80,7 @@ private[chisel3] class ErrorLog { /** Throw an exception if any errors have yet occurred. */ def checkpoint(): Unit = { + // scalastyle:off line.size.limit regex deprecations.foreach { case ((message, sourceLoc), count) => println(s"${ErrorLog.depTag} $sourceLoc ($count calls): $message") } @@ -112,6 +113,7 @@ private[chisel3] class ErrorLog { // No fatal errors, clear accumulated warnings since they've been reported errors.clear() } + // scalastyle:on line.size.limit regex } /** Returns the best guess at the first stack frame that belongs to user code. diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index c05d402d..0b0d1871 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -7,6 +7,8 @@ import core._ import chisel3.internal._ import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo} +// scalastyle:off number.of.types + case class PrimOp(val name: String) { override def toString: String = name } @@ -77,7 +79,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { protected def minWidth: Int if (forcedWidth) { require(widthArg.get >= minWidth, - s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") + s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") // scalastyle:ignore line.size.limit } } @@ -261,6 +263,7 @@ abstract class Definition extends Command { def id: HasId def name: String = id.getRef.name } +// scalastyle:off line.size.limit case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition diff --git a/coreMacros/src/main/scala/chisel3/SourceInfoDoc.scala b/coreMacros/src/main/scala/chisel3/SourceInfoDoc.scala index 2f14585e..4e7533d4 100644 --- a/coreMacros/src/main/scala/chisel3/SourceInfoDoc.scala +++ b/coreMacros/src/main/scala/chisel3/SourceInfoDoc.scala @@ -1,4 +1,4 @@ -// See LICENSE for license details +// See LICENSE for license details. package chisel3 diff --git a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala index 2f16083e..4977899a 100644 --- a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala +++ b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala @@ -13,6 +13,7 @@ import scala.reflect.macros.whitebox object RangeTransform class RangeTransform(val c: Context) { import c.universe._ + // scalastyle:off method.length line.size.limit def apply(args: c.Tree*): c.Tree = { val stringTrees = c.prefix.tree match { case q"$_(scala.StringContext.apply(..$strings))" => strings @@ -22,6 +23,7 @@ class RangeTransform(val c: Context) { case Literal(Constant(string: String)) => string case _ => c.abort(c.enclosingPosition, s"Range macro unable to parse StringContext element, got: ${showRaw(tree)}") } } + // scalastyle:on line.size.limit var nextStringIndex: Int = 1 var nextArgIndex: Int = 0 diff --git a/coreMacros/src/main/scala/chisel3/internal/RuntimeDeprecationTransform.scala b/coreMacros/src/main/scala/chisel3/internal/RuntimeDeprecationTransform.scala index 570e5383..1ba41a6d 100644 --- a/coreMacros/src/main/scala/chisel3/internal/RuntimeDeprecationTransform.scala +++ b/coreMacros/src/main/scala/chisel3/internal/RuntimeDeprecationTransform.scala @@ -22,7 +22,7 @@ class RuntimeDeprecatedTransform(val c: Context) { case q"new deprecated($desc, $since)" => desc } match { // ensure there's only one and return it case msg :: Nil => msg - case _ => c.abort(c.enclosingPosition, s"@chiselRuntimeDeprecated annotion must be used with exactly one @deprecated annotation, got annotations $annotations") + case _ => c.abort(c.enclosingPosition, s"@chiselRuntimeDeprecated annotion must be used with exactly one @deprecated annotation, got annotations $annotations") // scalastyle:ignore line.size.limit } val message = s"$tname is deprecated: $annotationMessage" val transformedExpr = q""" { @@ -31,7 +31,7 @@ class RuntimeDeprecatedTransform(val c: Context) { } """ q"$mods def $tname[..$tparams](...$paramss): $tpt = $transformedExpr" } - case other => c.abort(c.enclosingPosition, s"@chiselRuntimeDeprecated annotion may only be used on defs, got ${showCode(other)}") + case other => c.abort(c.enclosingPosition, s"@chiselRuntimeDeprecated annotion may only be used on defs, got ${showCode(other)}") // scalastyle:ignore line.size.limit }) q"..$transformed" } diff --git a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/NamingAnnotations.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/NamingAnnotations.scala index 29b27b9e..fba526af 100644 --- a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/NamingAnnotations.scala +++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/NamingAnnotations.scala @@ -62,7 +62,7 @@ class NamingTransforms(val c: Context) { trait ValNameTransformer extends Transformer { val contextVar: TermName - override def transform(tree: Tree) = tree match { + override def transform(tree: Tree): Tree = tree match { // Intentionally not prefixed with $mods, since modifiers usually mean the val definition // is in a non-transformable location, like as a parameter list. // TODO: is this exhaustive / correct in all cases? @@ -79,8 +79,8 @@ class NamingTransforms(val c: Context) { * classes and applies the naming transform on inner functions. */ class ModuleTransformer(val contextVar: TermName) extends ValNameTransformer { - override def transform(tree: Tree) = tree match { - case q"$mods class $tpname[..$tparams] $ctorMods(...$paramss) extends { ..$earlydefns } with ..$parents { $self => ..$stats }" => + override def transform(tree: Tree): Tree = tree match { + case q"$mods class $tpname[..$tparams] $ctorMods(...$paramss) extends { ..$earlydefns } with ..$parents { $self => ..$stats }" => // scalastyle:ignore line.size.limit tree // don't recurse into inner classes case q"$mods trait $tpname[..$tparams] extends { ..$earlydefns } with ..$parents { $self => ..$stats }" => tree // don't recurse into inner classes @@ -105,7 +105,7 @@ class NamingTransforms(val c: Context) { /** Method-specific val name transform, handling the return case. */ class MethodTransformer(val contextVar: TermName) extends ValNameTransformer { - override def transform(tree: Tree) = tree match { + override def transform(tree: Tree): Tree = tree match { // TODO: better error messages when returning nothing case q"return $expr" => q"return $globalNamingStack.pop_return_context($expr, $contextVar)" // Do not recurse into methods @@ -117,7 +117,7 @@ class NamingTransforms(val c: Context) { /** Applies the val name transform to a module body. Pretty straightforward, since Module is * the naming top level. */ - def transformModuleBody(stats: List[c.Tree]) = { + def transformModuleBody(stats: List[c.Tree]): Tree = { val contextVar = TermName(c.freshName("namingContext")) val transformedBody = (new ModuleTransformer(contextVar)).transformTrees(stats) @@ -132,7 +132,7 @@ class NamingTransforms(val c: Context) { /** Applies the val name transform to a method body, doing additional bookkeeping with the * context to allow names to propagate and prefix through the function call stack. */ - def transformHierarchicalMethod(expr: c.Tree) = { + def transformHierarchicalMethod(expr: c.Tree): Tree = { val contextVar = TermName(c.freshName("namingContext")) val transformedBody = (new MethodTransformer(contextVar)).transform(expr) @@ -161,6 +161,7 @@ class NamingTransforms(val c: Context) { var namedElts: Int = 0 val transformed = annottees.map(annottee => annottee match { + // scalastyle:off line.size.limit case q"$mods class $tpname[..$tparams] $ctorMods(...$paramss) extends { ..$earlydefns } with ..$parents { $self => ..$stats }" => { val transformedStats = transformModuleBody(stats) namedElts += 1 @@ -181,20 +182,21 @@ class NamingTransforms(val c: Context) { if (namedElts != 1) { c.abort(c.enclosingPosition, s"@chiselName annotation did not match exactly one valid tree, got:\r\n${annottees.map(tree => showCode(tree)).mkString("\r\n\r\n")}") } + // scalastyle:on line.size.limit q"..$transformed" } } @compileTimeOnly("enable macro paradise to expand macro annotations") -class dump extends StaticAnnotation { +class dump extends StaticAnnotation { // scalastyle:ignore class.name def macroTransform(annottees: Any*): Any = macro chisel3.internal.naming.DebugTransforms.dump } @compileTimeOnly("enable macro paradise to expand macro annotations") -class treedump extends StaticAnnotation { +class treedump extends StaticAnnotation { // scalastyle:ignore class.name def macroTransform(annottees: Any*): Any = macro chisel3.internal.naming.DebugTransforms.treedump } @compileTimeOnly("enable macro paradise to expand macro annotations") -class chiselName extends StaticAnnotation { +class chiselName extends StaticAnnotation { // scalastyle:ignore class.name def macroTransform(annottees: Any*): Any = macro chisel3.internal.naming.NamingTransforms.chiselName } diff --git a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala index aa474cb6..48036ce7 100644 --- a/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala +++ b/coreMacros/src/main/scala/chisel3/internal/sourceinfo/SourceInfoTransform.scala @@ -22,7 +22,7 @@ import scala.reflect.macros.whitebox trait SourceInfoTransformMacro { val c: Context import c.universe._ - def thisObj = c.prefix.tree + def thisObj: Tree = c.prefix.tree def implicitSourceInfo = q"implicitly[_root_.chisel3.internal.sourceinfo.SourceInfo]" def implicitCompileOptions = q"implicitly[_root_.chisel3.core.CompileOptions]" } @@ -94,10 +94,10 @@ abstract class AutoSourceTransform extends SourceInfoTransformMacro { /** Returns the TermName of the transformed function, which is the applied function name with do_ * prepended. */ - def doFuncTerm = { + def doFuncTerm: TermName = { val funcName = c.macroApplication match { case q"$_.$funcName[..$_](...$_)" => funcName - case _ => throw new Exception(s"Chisel Internal Error: Could not resolve function name from macro application: ${showCode(c.macroApplication)}") + case _ => throw new Exception(s"Chisel Internal Error: Could not resolve function name from macro application: ${showCode(c.macroApplication)}") // scalastyle:ignore line.size.limit } TermName("do_" + funcName) } diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala index 77371443..01b9ad1c 100644 --- a/src/main/scala/chisel3/Driver.scala +++ b/src/main/scala/chisel3/Driver.scala @@ -178,7 +178,7 @@ object Driver extends BackendCompilationUtilities { * @param dut The device under test * @return An execution result with useful stuff, or failure with message */ - def execute( + def execute( // scalastyle:ignore method.length optionsManager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions, dut: () => RawModule): ChiselExecutionResult = { val circuitOpt = try { @@ -192,7 +192,7 @@ object Driver extends BackendCompilationUtilities { ce.printStackTrace(new PrintWriter(sw)) sw.toString } - Predef.augmentString(stackTrace).lines.foreach(line => println(s"${ErrorLog.errTag} $line")) + Predef.augmentString(stackTrace).lines.foreach(line => println(s"${ErrorLog.errTag} $line")) // scalastyle:ignore regex line.size.limit None } diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala index 474058be..ad49b095 100644 --- a/src/main/scala/chisel3/compatibility.scala +++ b/src/main/scala/chisel3/compatibility.scala @@ -4,7 +4,7 @@ * while moving to the more standard package naming convention `chisel3` (lowercase c). */ -package object Chisel { // scalastyle:ignore package.object.name +package object Chisel { // scalastyle:ignore package.object.name number.of.types number.of.methods import chisel3.internal.firrtl.Width import scala.language.experimental.macros @@ -389,7 +389,7 @@ package object Chisel { // scalastyle:ignore package.object.name // Deprecated as of Chsiel3 @throws(classOf[Exception]) object throwException { - def apply(s: String, t: Throwable = null) = { + def apply(s: String, t: Throwable = null): Nothing = { val xcpt = new Exception(s, t) throw xcpt } diff --git a/src/main/scala/chisel3/internal/firrtl/Converter.scala b/src/main/scala/chisel3/internal/firrtl/Converter.scala index 181bdfe8..ee9d3a99 100644 --- a/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -42,7 +42,7 @@ private[chisel3] object Converter { // TODO // * Memoize? // * Move into the Chisel IR? - def convert(arg: Arg, ctx: Component): fir.Expression = arg match { + def convert(arg: Arg, ctx: Component): fir.Expression = arg match { // scalastyle:ignore cyclomatic.complexity case Node(id) => convert(id.getRef, ctx) case Ref(name) => @@ -54,8 +54,10 @@ private[chisel3] object Converter { case Index(imm, value) => fir.SubAccess(convert(imm, ctx), convert(value, ctx), fir.UnknownType) case ModuleIO(mod, name) => + // scalastyle:off if.brace if (mod eq ctx.id) fir.Reference(name, fir.UnknownType) else fir.SubField(fir.Reference(mod.getRef.name, fir.UnknownType), name, fir.UnknownType) + // scalastyle:on if.brace case u @ ULit(n, UnknownWidth()) => fir.UIntLiteral(n, fir.IntWidth(u.minWidth)) case ULit(n, w) => @@ -75,7 +77,7 @@ private[chisel3] object Converter { } /** Convert Commands that map 1:1 to Statements */ - def convertSimpleCommand(cmd: Command, ctx: Component): Option[fir.Statement] = cmd match { + def convertSimpleCommand(cmd: Command, ctx: Component): Option[fir.Statement] = cmd match { // scalastyle:ignore cyclomatic.complexity line.size.limit case e: DefPrim[_] => val consts = e.args.collect { case ILit(i) => i } val args = e.args.flatMap { @@ -145,8 +147,9 @@ private[chisel3] object Converter { * @param ctx Component (Module) context within which we are translating * @return FIRRTL Statement that is equivalent to the input cmds */ - def convert(cmds: Seq[Command], ctx: Component): fir.Statement = { + def convert(cmds: Seq[Command], ctx: Component): fir.Statement = { // scalastyle:ignore cyclomatic.complexity @tailrec + // scalastyle:off if.brace def rec(acc: Queue[fir.Statement], scope: List[WhenFrame]) (cmds: Seq[Command]): Seq[fir.Statement] = { @@ -190,6 +193,7 @@ private[chisel3] object Converter { } } } + // scalastyle:on if.brace fir.Block(rec(Queue.empty, List.empty)(cmds)) } @@ -209,7 +213,7 @@ private[chisel3] object Converter { case d => d.specifiedDirection } - def extractType(data: Data, clearDir: Boolean = false): fir.Type = data match { + def extractType(data: Data, clearDir: Boolean = false): fir.Type = data match { // scalastyle:ignore cyclomatic.complexity line.size.limit case _: Clock => fir.ClockType case d: EnumType => fir.UIntType(convert(d.width)) case d: UInt => fir.UIntType(convert(d.width)) diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 68513423..050c8b72 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -26,7 +26,7 @@ private class Emitter(circuit: Circuit) { s"$dirString ${e.id.getRef.name} : ${emitType(e.id, clearDir)}" } - private def emitType(d: Data, clearDir: Boolean = false): String = d match { + private def emitType(d: Data, clearDir: Boolean = false): String = d match { // scalastyle:ignore cyclomatic.complexity line.size.limit case d: Clock => "Clock" case d: chisel3.core.EnumType => s"UInt${d.width}" case d: UInt => s"UInt${d.width}" @@ -55,15 +55,15 @@ private class Emitter(circuit: Circuit) { case d => d.specifiedDirection } - private def emit(e: Command, ctx: Component): String = { + private def emit(e: Command, ctx: Component): String = { // scalastyle:ignore cyclomatic.complexity val firrtlLine = e match { case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).mkString(", ")})" case e: DefWire => s"wire ${e.name} : ${emitType(e.id)}" case e: DefReg => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)}" - case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" + case e: DefRegInit => s"reg ${e.name} : ${emitType(e.id)}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" // scalastyle:ignore line.size.limit case e: DefMemory => s"cmem ${e.name} : ${emitType(e.t)}[${e.size}]" case e: DefSeqMemory => s"smem ${e.name} : ${emitType(e.t)}[${e.size}]" - case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" + case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" // scalastyle:ignore line.size.limit case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" case e: Attach => e.locs.map(_.fullName(ctx)).mkString("attach (", ", ", ")") @@ -94,6 +94,7 @@ private class Emitter(circuit: Circuit) { s"skip" } firrtlLine + e.sourceInfo.makeMessage(" " + _) + // scalastyle:on line.size.limit } private def emitParam(name: String, p: Param): String = { diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index 6c1ab588..e75184db 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -79,7 +79,7 @@ package object chisel3 { // scalastyle:ignore package.object.name implicit class cloneTypeable[T <: Data](target: T) { @chiselRuntimeDeprecated - @deprecated("chiselCloneType is deprecated, use chiselTypeOf(...) to get the Chisel Type of a hardware object", "chisel3") + @deprecated("chiselCloneType is deprecated, use chiselTypeOf(...) to get the Chisel Type of a hardware object", "chisel3") // scalastyle:ignore line.size.limit def chiselCloneType: T = { target.cloneTypeFull.asInstanceOf[T] } @@ -462,7 +462,7 @@ package object chisel3 { // scalastyle:ignore package.object.name * q2_io.enq <> q1.io.deq * }}} */ - def apply(proto: BaseModule)(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: chisel3.core.CompileOptions): ClonePorts = { + def apply(proto: BaseModule)(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: chisel3.core.CompileOptions): ClonePorts = { // scalastyle:ignore line.size.limit chisel3.core.BaseModule.cloneIORecord(proto) } } diff --git a/src/main/scala/chisel3/testers/package.scala b/src/main/scala/chisel3/testers/package.scala index 649ea3d7..ad1c523d 100644 --- a/src/main/scala/chisel3/testers/package.scala +++ b/src/main/scala/chisel3/testers/package.scala @@ -7,4 +7,4 @@ package chisel3 */ package object testers { -}
\ No newline at end of file +} diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala index 956b8262..1692e083 100644 --- a/src/main/scala/chisel3/util/Bitwise.scala +++ b/src/main/scala/chisel3/util/Bitwise.scala @@ -90,7 +90,7 @@ object Fill { * }}} */ object Reverse { - private def doit(in: UInt, length: Int): UInt = length match { + private def doit(in: UInt, length: Int): UInt = length match { // scalastyle:ignore cyclomatic.complexity case _ if length < 0 => throw new IllegalArgumentException(s"length (=$length) must be nonnegative integer.") case _ if length <= 1 => in case _ if isPow2(length) && length >= 8 && length <= 64 => diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 105b4528..7ab13922 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -95,7 +95,7 @@ object Decoupled */ @chiselName def apply[T <: Data](irr: IrrevocableIO[T]): DecoupledIO[T] = { - require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") + require(DataMirror.directionOf(irr.bits) == Direction.Output, "Only safe to cast produced Irrevocable bits to Decoupled.") // scalastyle:ignore line.size.limit val d = Wire(new DecoupledIO(irr.bits)) d.bits := irr.bits d.valid := irr.valid @@ -126,7 +126,7 @@ object Irrevocable * @note unsafe (and will error) on the consumer (output) side of an DecoupledIO */ def apply[T <: Data](dec: DecoupledIO[T]): IrrevocableIO[T] = { - require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.") + require(DataMirror.directionOf(dec.bits) == Direction.Input, "Only safe to cast consumed Decoupled bits to Irrevocable.") // scalastyle:ignore line.size.limit val i = Wire(new IrrevocableIO(dec.bits)) dec.bits := i.bits dec.valid := i.valid diff --git a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala index e88d475e..853d82af 100644 --- a/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala +++ b/src/test/scala/chiselTests/AnnotatingDiamondSpec.scala @@ -6,7 +6,7 @@ import chisel3._ import chisel3.experimental.{annotate, ChiselAnnotation, RunFirrtlTransform} import chisel3.internal.InstanceId import chisel3.testers.BasicTester -import firrtl.{CircuitState, LowForm, Transform} +import firrtl.{CircuitForm, CircuitState, LowForm, Transform} import firrtl.annotations.{ Annotation, SingleTargetAnnotation, @@ -19,15 +19,15 @@ import org.scalatest._ * Chisel/Firrtl library */ case class IdentityAnnotation(target: Named, value: String) extends SingleTargetAnnotation[Named] { - def duplicate(n: Named) = this.copy(target = n) + def duplicate(n: Named): IdentityAnnotation = this.copy(target = n) } /** ChiselAnnotation that corresponds to the above FIRRTL annotation */ case class IdentityChiselAnnotation(target: InstanceId, value: String) extends ChiselAnnotation with RunFirrtlTransform { - def toFirrtl = IdentityAnnotation(target.toNamed, value) - def transformClass = classOf[IdentityTransform] + def toFirrtl: IdentityAnnotation = IdentityAnnotation(target.toNamed, value) + def transformClass: Class[IdentityTransform] = classOf[IdentityTransform] } -object identify { +object identify { // scalastyle:ignore object.name def apply(component: InstanceId, value: String): Unit = { val anno = IdentityChiselAnnotation(component, value) annotate(anno) @@ -35,8 +35,8 @@ object identify { } class IdentityTransform extends Transform { - def inputForm = LowForm - def outputForm = LowForm + def inputForm: CircuitForm = LowForm + def outputForm: CircuitForm = LowForm def execute(state: CircuitState): CircuitState = { val annosx = state.annotations.map { diff --git a/src/test/scala/chiselTests/AnnotationNoDedup.scala b/src/test/scala/chiselTests/AnnotationNoDedup.scala index d93da31f..0f195fdf 100644 --- a/src/test/scala/chiselTests/AnnotationNoDedup.scala +++ b/src/test/scala/chiselTests/AnnotationNoDedup.scala @@ -46,6 +46,7 @@ class UsesMuchUsedModule(addAnnos: Boolean) extends Module { } class AnnotationNoDedup extends FreeSpec with Matchers { + // scalastyle:off line.size.limit "Firrtl provides transform that reduces identical modules to a single instance" - { "Annotations can be added which will prevent this deduplication for specific modules instances" in { Driver.execute(Array("-X", "low", "--target-dir", "test_run_dir"), () => new UsesMuchUsedModule(addAnnos = true)) match { @@ -74,4 +75,5 @@ class AnnotationNoDedup extends FreeSpec with Matchers { } } } + // scalastyle:on line.size.limit } diff --git a/src/test/scala/chiselTests/AutoClonetypeSpec.scala b/src/test/scala/chiselTests/AutoClonetypeSpec.scala index cf88fd2e..75fb46b8 100644 --- a/src/test/scala/chiselTests/AutoClonetypeSpec.scala +++ b/src/test/scala/chiselTests/AutoClonetypeSpec.scala @@ -25,7 +25,7 @@ class BaseBundleVal(val i: Int) extends Bundle { class SubBundle(i: Int, val i2: Int) extends BaseBundleVal(i) { val inner2 = UInt(i2.W) } -class SubBundleInvalid(i: Int, val i2: Int) extends BaseBundleVal(i+1) { +class SubBundleInvalid(i: Int, val i2: Int) extends BaseBundleVal(i + 1) { val inner2 = UInt(i2.W) } @@ -164,7 +164,7 @@ class AutoClonetypeSpec extends ChiselFlatSpec { "3.0 null compatibility" should "not need clonetype" in { elaborate { new Module { class InnerClassThing { - def createBundle = new Bundle { + def createBundle: Bundle = new Bundle { val a = Output(UInt(8.W)) } } diff --git a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala index fc8eb73b..7533b873 100644 --- a/src/test/scala/chiselTests/AutoNestedCloneSpec.scala +++ b/src/test/scala/chiselTests/AutoNestedCloneSpec.scala @@ -21,7 +21,7 @@ class AutoNestedCloneSpec extends ChiselFlatSpec with Matchers { class InnerIOType extends Bundle { val in = Input(UInt(w.W)) } - def getIO = new InnerIOType + def getIO: InnerIOType = new InnerIOType } val io = IO(new Bundle {}) val myWire = Wire((new Middle(w)).getIO) @@ -107,7 +107,7 @@ class AutoNestedCloneSpec extends ChiselFlatSpec with Matchers { intercept[ChiselException] { elaborate { class Outer(val w: Int) extends Module { class Middle(val w: Int) { - def getIO = new Bundle { + def getIO: Bundle = new Bundle { val in = Input(UInt(w.W)) } } diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala index d8fc70ac..1b91da3c 100644 --- a/src/test/scala/chiselTests/BetterNamingTests.scala +++ b/src/test/scala/chiselTests/BetterNamingTests.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + package chiselTests import collection.mutable diff --git a/src/test/scala/chiselTests/BoringUtilsSpec.scala b/src/test/scala/chiselTests/BoringUtilsSpec.scala index 06840577..80bea3a0 100644 --- a/src/test/scala/chiselTests/BoringUtilsSpec.scala +++ b/src/test/scala/chiselTests/BoringUtilsSpec.scala @@ -11,7 +11,7 @@ import chisel3.experimental.{BaseModule, ChiselAnnotation, MultiIOModule, RawMod import chisel3.util.experimental.BoringUtils import firrtl.{CircuitForm, CircuitState, ChirrtlForm, Transform} -import firrtl.annotations.NoTargetAnnotation +import firrtl.annotations.{Annotation, NoTargetAnnotation} import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation} import firrtl.passes.wiring.WiringException @@ -51,7 +51,9 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners { trait WireX { this: BaseModule => val x = Wire(UInt(4.W)) - chisel3.experimental.annotate(new ChiselAnnotation{ def toFirrtl = DontTouchAnnotation(x.toNamed) }) + chisel3.experimental.annotate(new ChiselAnnotation { + def toFirrtl: Annotation = DontTouchAnnotation(x.toNamed) + }) } class Source extends RawModule with WireX { @@ -77,8 +79,9 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners { sinks.zip(Seq(0, 1, 1, 2, 2, 2)).map{ case (a, b) => chisel3.assert(a.out === b.U) } } - /** This is testing a complicated wiring pattern and exercising the necessity of disabling deduplication for sources and - * sinks. Without disabling deduplication, this test will fail. + /** This is testing a complicated wiring pattern and exercising + * the necessity of disabling deduplication for sources and sinks. + * Without disabling deduplication, this test will fail. */ class TopTester extends ShouldntAssertTester { val dut = Module(new Top(4)) @@ -90,14 +93,14 @@ class BoringUtilsSpec extends ChiselFlatSpec with ChiselRunners { case object FooAnnotation extends NoTargetAnnotation chisel3.experimental.annotate( new ChiselAnnotation with RunFirrtlTransform { - def toFirrtl = FooAnnotation - def transformClass = classOf[StripNoDedupAnnotation] } ) + def toFirrtl: Annotation = FooAnnotation + def transformClass: Class[_ <: Transform] = classOf[StripNoDedupAnnotation] } ) } behavior of "BoringUtils.bore" it should "connect across modules using BoringUtils.bore" in { - runTester(new TopTester) should be (true) + runTester(new TopTester) should be (true) } it should "throw an exception if NoDedupAnnotations are removed" in { diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala index 7d28660b..9db602ee 100644 --- a/src/test/scala/chiselTests/BundleLiteralSpec.scala +++ b/src/test/scala/chiselTests/BundleLiteralSpec.scala @@ -18,7 +18,7 @@ class BundleLiteralSpec extends ChiselFlatSpec { import chisel3.core.BundleLitBinding import chisel3.internal.firrtl.{ULit, Width} // Full bundle literal constructor - def Lit(aVal: UInt, bVal: Bool): MyBundle = { + def Lit(aVal: UInt, bVal: Bool): MyBundle = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.a -> litArgOfBits(aVal), @@ -27,7 +27,7 @@ class BundleLiteralSpec extends ChiselFlatSpec { clone } // Partial bundle literal constructor - def Lit(aVal: UInt): MyBundle = { + def Lit(aVal: UInt): MyBundle = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.a -> litArgOfBits(aVal) diff --git a/src/test/scala/chiselTests/BundleSpec.scala b/src/test/scala/chiselTests/BundleSpec.scala index 502134b4..4fc7d7d0 100644 --- a/src/test/scala/chiselTests/BundleSpec.scala +++ b/src/test/scala/chiselTests/BundleSpec.scala @@ -10,25 +10,25 @@ trait BundleSpecUtils { class BundleFooBar extends Bundle { val foo = UInt(16.W) val bar = UInt(16.W) - override def cloneType = (new BundleFooBar).asInstanceOf[this.type] + override def cloneType: this.type = (new BundleFooBar).asInstanceOf[this.type] } class BundleBarFoo extends Bundle { val bar = UInt(16.W) val foo = UInt(16.W) - override def cloneType = (new BundleBarFoo).asInstanceOf[this.type] + override def cloneType: this.type = (new BundleBarFoo).asInstanceOf[this.type] } class BundleFoo extends Bundle { val foo = UInt(16.W) - override def cloneType = (new BundleFoo).asInstanceOf[this.type] + override def cloneType: this.type = (new BundleFoo).asInstanceOf[this.type] } class BundleBar extends Bundle { val bar = UInt(16.W) - override def cloneType = (new BundleBar).asInstanceOf[this.type] + override def cloneType: this.type = (new BundleBar).asInstanceOf[this.type] } class BadSeqBundle extends Bundle { val bar = Seq(UInt(16.W), UInt(8.W), UInt(4.W)) - override def cloneType = (new BadSeqBundle).asInstanceOf[this.type] + override def cloneType: this.type = (new BadSeqBundle).asInstanceOf[this.type] } class MyModule(output: Bundle, input: Bundle) extends Module { diff --git a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala index 95dc87c1..02b35734 100644 --- a/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala @@ -13,11 +13,11 @@ object CompatibilityComponents { val a = UInt(width = 32) val b = UInt(width = 32).flip - override def cloneType = (new ChiselBundle).asInstanceOf[this.type] + override def cloneType: this.type = (new ChiselBundle).asInstanceOf[this.type] } class ChiselRecord extends Record { val elements = ListMap("a" -> UInt(width = 32), "b" -> UInt(width = 32).flip) - override def cloneType = (new ChiselRecord).asInstanceOf[this.type] + override def cloneType: this.type = (new ChiselRecord).asInstanceOf[this.type] } abstract class ChiselDriverModule(_io: => Record) extends Module { @@ -49,12 +49,12 @@ object Chisel3Components { val a = Output(UInt(32.W)) val b = Input(UInt(32.W)) - override def cloneType = (new Chisel3Bundle).asInstanceOf[this.type] + override def cloneType: this.type = (new Chisel3Bundle).asInstanceOf[this.type] } class Chisel3Record extends Record { val elements = ListMap("a" -> Output(UInt(32.W)), "b" -> Input(UInt(32.W))) - override def cloneType = (new Chisel3Record).asInstanceOf[this.type] + override def cloneType: this.type = (new Chisel3Record).asInstanceOf[this.type] } abstract class Chisel3DriverModule(_io: => Record) extends Module { diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala index 339f2af1..57cb5ec3 100644 --- a/src/test/scala/chiselTests/CompatibilitySpec.scala +++ b/src/test/scala/chiselTests/CompatibilitySpec.scala @@ -47,7 +47,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks val value: Int = Gen.choose(2, 2048).sample.get log2Up(value) shouldBe (1 max BigInt(value - 1).bitLength) log2Ceil(value) shouldBe (BigInt(value - 1).bitLength) - log2Down(value) shouldBe ((1 max BigInt(value - 1).bitLength) - (if (value > 0 && ((value & (value - 1)) == 0)) 0 else 1)) + log2Down(value) shouldBe ((1 max BigInt(value - 1).bitLength) - (if (value > 0 && ((value & (value - 1)) == 0)) 0 else 1)) // scalastyle:ignore line.size.limit log2Floor(value) shouldBe (BigInt(value - 1).bitLength - (if (value > 0 && ((value & (value - 1)) == 0)) 0 else 1)) isPow2(BigInt(1) << value) shouldBe true isPow2((BigInt(1) << value) - 1) shouldBe false @@ -189,6 +189,7 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type] } + // scalastyle:off line.size.limit "A Module with missing bundle fields when compiled with the Chisel compatibility package" should "not throw an exception" in { class ConnectFieldMismatchModule extends Module { @@ -335,5 +336,5 @@ class CompatibiltySpec extends ChiselFlatSpec with GeneratorDrivenPropertyChecks Chisel.assert(io.bar.dir == INPUT) }) } - + // scalastyle:on line.size.limit } diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala index 299ce4dd..4f647442 100644 --- a/src/test/scala/chiselTests/CompileOptionsTest.scala +++ b/src/test/scala/chiselTests/CompileOptionsTest.scala @@ -21,6 +21,7 @@ class CompileOptionsSpec extends ChiselFlatSpec { override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type] } + // scalastyle:off line.size.limit "A Module with missing bundle fields when compiled with implicit Strict.CompileOption " should "throw an exception" in { a [ChiselException] should be thrownBy { import chisel3.core.ExplicitCompileOptions.Strict @@ -184,4 +185,5 @@ class CompileOptionsSpec extends ChiselFlatSpec { } elaborate { new DirectionLessConnectionModule() } } + // scalastyle:on line.size.limit } diff --git a/src/test/scala/chiselTests/DataPrint.scala b/src/test/scala/chiselTests/DataPrint.scala index 662d8e1a..bec722f3 100644 --- a/src/test/scala/chiselTests/DataPrint.scala +++ b/src/test/scala/chiselTests/DataPrint.scala @@ -22,7 +22,7 @@ class DataPrintSpec extends ChiselFlatSpec with Matchers { import chisel3.core.BundleLitBinding import chisel3.internal.firrtl.{ULit, Width} // Full bundle literal constructor - def Lit(aVal: UInt, bVal: Bool): BundleTest = { + def Lit(aVal: UInt, bVal: Bool): BundleTest = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.a -> litArgOfBits(aVal), diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala index 94e54760..db569233 100644 --- a/src/test/scala/chiselTests/EnableShiftRegister.scala +++ b/src/test/scala/chiselTests/EnableShiftRegister.scala @@ -23,6 +23,7 @@ class EnableShiftRegister extends Module { io.out := r3 } +// scalastyle:off regex /* class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) { val reg = Array.fill(4){ 0 } @@ -42,6 +43,7 @@ class EnableShiftRegisterTester(c: EnableShiftRegister) extends Tester(c) { } } */ +// scalastyle:on regex class EnableShiftRegisterSpec extends ChiselPropSpec { diff --git a/src/test/scala/chiselTests/FixedPointSpec.scala b/src/test/scala/chiselTests/FixedPointSpec.scala index 137ffc76..a928f08e 100644 --- a/src/test/scala/chiselTests/FixedPointSpec.scala +++ b/src/test/scala/chiselTests/FixedPointSpec.scala @@ -84,12 +84,12 @@ class FixedPointMuxTester extends BasicTester { val unknownWidthLowPrecision = 6.0.F(0.BP) val unknownFixed = Wire(FixedPoint()) unknownFixed := smallWidthHighPrecision - + assert(Mux(true.B, largeWidthLowPrecision, smallWidthHighPrecision) === 6.0.F(0.BP)) assert(Mux(false.B, largeWidthLowPrecision, smallWidthHighPrecision) === 0.25.F(2.BP)) assert(Mux(false.B, largeWidthLowPrecision, unknownFixed) === 0.25.F(2.BP)) assert(Mux(true.B, unknownWidthLowPrecision, smallWidthHighPrecision) === 6.0.F(0.BP)) - + stop() } diff --git a/src/test/scala/chiselTests/InvalidateAPISpec.scala b/src/test/scala/chiselTests/InvalidateAPISpec.scala index c0a643cc..8dfb078b 100644 --- a/src/test/scala/chiselTests/InvalidateAPISpec.scala +++ b/src/test/scala/chiselTests/InvalidateAPISpec.scala @@ -21,6 +21,7 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila val out = Output(Bool()) } + // scalastyle:off line.size.limit property("an output connected to DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions") { import chisel3.core.ExplicitCompileOptions.Strict class ModuleWithDontCare extends Module { @@ -207,4 +208,5 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers with BackendCompila val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare) firrtlOutput should include("is invalid") } + // scalastyle:on line.size.limit } diff --git a/src/test/scala/chiselTests/LiteralExtractorSpec.scala b/src/test/scala/chiselTests/LiteralExtractorSpec.scala index 2879f2d9..25979488 100644 --- a/src/test/scala/chiselTests/LiteralExtractorSpec.scala +++ b/src/test/scala/chiselTests/LiteralExtractorSpec.scala @@ -63,7 +63,7 @@ class LiteralExtractorSpec extends ChiselFlatSpec { val y = FixedPoint(8.W, 4.BP) import chisel3.core.BundleLitBinding - def Lit(aVal: SInt, bVal: FixedPoint): InsideBundle = { + def Lit(aVal: SInt, bVal: FixedPoint): InsideBundle = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.x -> litArgOfBits(aVal), @@ -78,7 +78,7 @@ class LiteralExtractorSpec extends ChiselFlatSpec { // the following errors with "assertion failed" - println(outsideLiteral === insideLiteral) + println(outsideLiteral === insideLiteral) // scalastyle:ignore regex // chisel3.core.assert(outsideLiteral === insideLiteral) // the following lines of code error @@ -107,7 +107,7 @@ class LiteralExtractorSpec extends ChiselFlatSpec { // the future. import chisel3.core.BundleLitBinding import chisel3.internal.firrtl.{ULit, Width} - def Lit(aVal: UInt, bVal: Bool): MyBundle = { + def Lit(aVal: UInt, bVal: Bool): MyBundle = { // scalastyle:ignore method.name val clone = cloneType clone.selfBind(BundleLitBinding(Map( clone.a -> litArgOfBits(aVal), diff --git a/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala b/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala index b83557cc..c2c69bbf 100644 --- a/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala +++ b/src/test/scala/chiselTests/MissingCloneBindingExceptionSpec.scala @@ -13,7 +13,7 @@ class MissingCloneBindingExceptionSpec extends ChiselFlatSpec with Matchers { class TestIO(w: Int) extends Bundle { val a = Input(Vec(4, UInt(w.W))) } - + val io = IO(new TestIO(32)) } @@ -36,7 +36,7 @@ class MissingCloneBindingExceptionSpec extends ChiselFlatSpec with Matchers { class TestIO(w: Int) extends Bundle { val a = Vec(4, UInt(width = w)).asInput } - + val io = IO(new TestIO(32)) } diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala index a973412e..46e60064 100644 --- a/src/test/scala/chiselTests/Module.scala +++ b/src/test/scala/chiselTests/Module.scala @@ -70,7 +70,7 @@ class ModuleWrapper(gen: => Module) extends Module { class NullModuleWrapper extends Module { val io = IO(new Bundle{}) override lazy val desiredName = s"${child.desiredName}Wrapper" - println(s"My name is ${name}") + println(s"My name is ${name}") // scalastyle:ignore regex val child = Module(new ModuleWire) } diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala index 1e1d3f70..745e25de 100644 --- a/src/test/scala/chiselTests/MultiAssign.scala +++ b/src/test/scala/chiselTests/MultiAssign.scala @@ -40,7 +40,7 @@ class IllegalAssignSpec extends ChiselFlatSpec { }} } } - + "Reassignments to ops" should "be disallowed" in { intercept[chisel3.internal.ChiselException] { elaborate{ new BasicTester { @@ -48,7 +48,7 @@ class IllegalAssignSpec extends ChiselFlatSpec { }} } } - + "Reassignments to bit slices" should "be disallowed" in { intercept[chisel3.internal.ChiselException] { elaborate{ new BasicTester { @@ -56,7 +56,7 @@ class IllegalAssignSpec extends ChiselFlatSpec { }} } } - + "Bulk-connecting two read-only nodes" should "be disallowed" in { intercept[chisel3.internal.ChiselException] { elaborate{ new BasicTester { diff --git a/src/test/scala/chiselTests/MultiIOModule.scala b/src/test/scala/chiselTests/MultiIOModule.scala index 07e09041..7978970a 100644 --- a/src/test/scala/chiselTests/MultiIOModule.scala +++ b/src/test/scala/chiselTests/MultiIOModule.scala @@ -34,7 +34,7 @@ trait MultiIOTrait extends MultiIOModule { // Composition of the two above traits, example of IO composition directly using multiple top-level // IOs rather than indirectly by constraining the type of the single .io field. -class ComposedMultiIOModule extends MultiIOModule +class ComposedMultiIOModule extends MultiIOModule with LiteralOutputTrait with MultiIOTrait { val topModuleIO = IO(Input(UInt(32.W))) myTraitIO := topModuleIO diff --git a/src/test/scala/chiselTests/MuxSpec.scala b/src/test/scala/chiselTests/MuxSpec.scala index d06c00af..0ead960a 100644 --- a/src/test/scala/chiselTests/MuxSpec.scala +++ b/src/test/scala/chiselTests/MuxSpec.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + package chiselTests import chisel3._ @@ -22,4 +24,4 @@ class MuxSpec extends ChiselFlatSpec { "Mux" should "pass basic checks" in { assertTesterPasses { new MuxTester } } -}
\ No newline at end of file +} diff --git a/src/test/scala/chiselTests/NamingAnnotationTest.scala b/src/test/scala/chiselTests/NamingAnnotationTest.scala index ec0874fc..9fdf0695 100644 --- a/src/test/scala/chiselTests/NamingAnnotationTest.scala +++ b/src/test/scala/chiselTests/NamingAnnotationTest.scala @@ -54,7 +54,7 @@ trait NamedModuleTester extends MultiIOModule { @chiselName class NamedModule extends NamedModuleTester { @chiselName - def FunctionMockupInner(): UInt = { + def FunctionMockupInner(): UInt = { // scalastyle:ignore method.name val my2A = 1.U val my2B = expectName(my2A +& 2.U, "test_myNested_my2B") val my2C = my2B +& 3.U // should get named at enclosing scope @@ -62,7 +62,7 @@ class NamedModule extends NamedModuleTester { } @chiselName - def FunctionMockup(): UInt = { + def FunctionMockup(): UInt = { // scalastyle:ignore method.name val myNested = expectName(FunctionMockupInner(), "test_myNested") val myA = expectName(1.U + myNested, "test_myA") val myB = expectName(myA +& 2.U, "test_myB") @@ -76,14 +76,14 @@ class NamedModule extends NamedModuleTester { } // chiselName "implicitly" applied - def ImplicitlyNamed(): UInt = { + def ImplicitlyNamed(): UInt = { // scalastyle:ignore method.name val implicitA = expectName(1.U + 2.U, "test3_implicitA") val implicitB = expectName(implicitA + 3.U, "test3_implicitB") implicitB + 2.U // named at enclosing scope } // Ensure this applies a partial name if there is no return value - def NoReturnFunction() { + def NoReturnFunction() { // scalastyle:ignore method.name val noreturn = expectName(1.U + 2.U, "noreturn") } @@ -132,7 +132,7 @@ class NameCollisionModule extends NamedModuleTester { */ class NonNamedModule extends NamedModuleTester { @chiselName - def NamedFunction(): UInt = { + def NamedFunction(): UInt = { // scalastyle:ignore method.name val myVal = 1.U + 2.U myVal } @@ -145,12 +145,12 @@ class NonNamedModule extends NamedModuleTester { */ object NonNamedHelper { @chiselName - def NamedFunction(): UInt = { + def NamedFunction(): UInt = { // scalastyle:ignore method.name val myVal = 1.U + 2.U myVal } - def NonNamedFunction() : UInt = { + def NonNamedFunction() : UInt = { // scalastyle:ignore method.name val myVal = NamedFunction() myVal } diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala index 6ae38a24..7ba4bf5d 100644 --- a/src/test/scala/chiselTests/PrintableSpec.scala +++ b/src/test/scala/chiselTests/PrintableSpec.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + package chiselTests import org.scalatest.{FlatSpec, Matchers} @@ -105,10 +107,10 @@ class PrintableSpec extends FlatSpec with Matchers { } class MyBundle extends Bundle { val foo = UInt(32.W) - override def cloneType = (new MyBundle).asInstanceOf[this.type] + override def cloneType: this.type = (new MyBundle).asInstanceOf[this.type] } class MyModule extends BasicTester { - override def desiredName = "MyModule" + override def desiredName: String = "MyModule" val myWire = Wire(new MyBundle) val myInst = Module(new MySubModule) printf(p"${Name(myWire.foo)}") @@ -116,7 +118,7 @@ class PrintableSpec extends FlatSpec with Matchers { printf(p"${FullName(myInst.io.fizz)}") } val firrtl = Driver.emit(() => new MyModule) - println(firrtl) + println(firrtl) // scalastyle:ignore regex getPrintfs(firrtl) match { case Seq(Printf("foo", Seq()), Printf("myWire.foo", Seq()), diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala index 2eb7cfc8..bf6b92eb 100644 --- a/src/test/scala/chiselTests/RecordSpec.scala +++ b/src/test/scala/chiselTests/RecordSpec.scala @@ -18,7 +18,7 @@ final class CustomBundle(elts: (String, Data)*) extends Record { field -> elt }: _*) def apply(elt: String): Data = elements(elt) - override def cloneType = { + override def cloneType: this.type = { val cloned = elts.map { case (n, d) => n -> DataMirror.internal.chiselTypeClone(d) } (new CustomBundle(cloned: _*)).asInstanceOf[this.type] } @@ -28,11 +28,11 @@ trait RecordSpecUtils { class MyBundle extends Bundle { val foo = UInt(32.W) val bar = UInt(32.W) - override def cloneType = (new MyBundle).asInstanceOf[this.type] + override def cloneType: this.type = (new MyBundle).asInstanceOf[this.type] } // Useful for constructing types from CustomBundle // This is a def because each call to this needs to return a new instance - def fooBarType = new CustomBundle("foo" -> UInt(32.W), "bar" -> UInt(32.W)) + def fooBarType: CustomBundle = new CustomBundle("foo" -> UInt(32.W), "bar" -> UInt(32.W)) class MyModule(output: => Record, input: => Record) extends Module { val io = IO(new Bundle { diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala index 07efb7dc..21b638e5 100644 --- a/src/test/scala/chiselTests/Risc.scala +++ b/src/test/scala/chiselTests/Risc.scala @@ -54,6 +54,7 @@ class Risc extends Module { } } +// scalastyle:off regex /* class RiscTester(c: Risc) extends Tester(c) { def wr(addr: BigInt, data: BigInt) = { @@ -111,6 +112,7 @@ class RiscTester(c: Risc) extends Tester(c) { expect(c.io.out, 4) } */ +// scalastyle:on regex class RiscSpec extends ChiselPropSpec { diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala index 3cdb68eb..9f17c741 100644 --- a/src/test/scala/chiselTests/Stack.scala +++ b/src/test/scala/chiselTests/Stack.scala @@ -17,7 +17,7 @@ class ChiselStack(val depth: Int) extends Module { }) val stack_mem = Mem(depth, UInt(32.W)) - val sp = RegInit(0.U(log2Ceil(depth+1).W)) + val sp = RegInit(0.U(log2Ceil(depth + 1).W)) val out = RegInit(0.U(32.W)) when (io.en) { diff --git a/src/test/scala/chiselTests/StrongEnum.scala b/src/test/scala/chiselTests/StrongEnum.scala index d38aa1e4..f5c3bc2f 100644 --- a/src/test/scala/chiselTests/StrongEnum.scala +++ b/src/test/scala/chiselTests/StrongEnum.scala @@ -7,7 +7,7 @@ import chisel3.experimental.ChiselEnum import chisel3.internal.firrtl.UnknownWidth import chisel3.util._ import chisel3.testers.BasicTester -import org.scalatest.{FreeSpec, Matchers} +import org.scalatest.{Assertion, FreeSpec, Matchers} object EnumExample extends ChiselEnum { val e0, e1, e2 = Value @@ -252,7 +252,7 @@ class StrongEnumFSMTester extends BasicTester { // Inputs and expected results val inputs: Vec[Bool] = VecInit(false.B, true.B, false.B, true.B, true.B, true.B, false.B, true.B, true.B, false.B) - val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) + val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) // scalastyle:ignore line.size.limit val expected_state = VecInit(sNone, sNone, sOne1, sNone, sOne1, sTwo1s, sTwo1s, sNone, sOne1, sTwo1s) val cntr = Counter(inputs.length) @@ -331,7 +331,7 @@ class StrongEnumSpec extends ChiselFlatSpec { elaborate(new CastFromNonLitWidth) } - for (w <- (EnumExample.getWidth+1) to (EnumExample.getWidth+100)) { + for (w <- (EnumExample.getWidth + 1) to (EnumExample.getWidth + 100)) { a [ChiselException] should be thrownBy { elaborate(new CastFromNonLitWidth(Some(w))) } @@ -361,7 +361,7 @@ class StrongEnumSpec extends ChiselFlatSpec { } it should "maintain Scala-level type-safety" in { - def foo(e: EnumExample.Type) = {} + def foo(e: EnumExample.Type): Unit = {} "foo(EnumExample.e1); foo(EnumExample.e1.next)" should compile "foo(OtherEnum.otherEnum)" shouldNot compile @@ -378,7 +378,8 @@ class StrongEnumAnnotationSpec extends ChiselFlatSpec { ignore should "Test that strong enums annotate themselves appropriately" in { - def test() = { + // scalastyle:off regex + def test(): Assertion = {// scalastyle:ignore cyclomatic.complexity Driver.execute(Array("--target-dir", "test_run_dir"), () => new StrongEnumFSM) match { case ChiselExecutionSuccess(Some(circuit), emitted, _) => val annos = circuit.annotations.map(_.toFirrtl) @@ -421,6 +422,7 @@ class StrongEnumAnnotationSpec extends ChiselFlatSpec { case _ => assert(false) } + // scalastyle:on regex } // We run this test twice, to test for an older bug where only the first circuit would be annotated diff --git a/src/test/scala/chiselTests/Util.scala b/src/test/scala/chiselTests/Util.scala index 80e37285..82ae7072 100644 --- a/src/test/scala/chiselTests/Util.scala +++ b/src/test/scala/chiselTests/Util.scala @@ -1,3 +1,5 @@ +// See LICENSE for license details. + // Useful utilities for tests package chiselTests diff --git a/src/test/scala/chiselTests/WidthSpec.scala b/src/test/scala/chiselTests/WidthSpec.scala index 4fcebb32..0e76fdca 100644 --- a/src/test/scala/chiselTests/WidthSpec.scala +++ b/src/test/scala/chiselTests/WidthSpec.scala @@ -70,11 +70,11 @@ abstract class WireRegWidthSpecImpl extends ChiselFlatSpec { } class WireWidthSpec extends WireRegWidthSpecImpl { - def name = "Wire" + def name: String = "Wire" def builder[T <: Data](x: T): T = Wire(x) } class RegWidthSpec extends WireRegWidthSpecImpl { - def name = "Reg" + def name: String = "Reg" def builder[T <: Data](x: T): T = Reg(x) } @@ -175,13 +175,13 @@ abstract class WireDefaultRegInitSpecImpl extends ChiselFlatSpec { } class WireDefaultWidthSpec extends WireDefaultRegInitSpecImpl { - def name = "WireDefault" + def name: String = "WireDefault" def builder1[T <: Data](x: T): T = WireDefault(x) def builder2[T <: Data](x: T, y: T): T = WireDefault(x, y) } class RegInitWidthSpec extends WireDefaultRegInitSpecImpl { - def name = "RegInit" + def name: String = "RegInit" def builder1[T <: Data](x: T): T = RegInit(x) def builder2[T <: Data](x: T, y: T): T = RegInit(x, y) } diff --git a/src/test/scala/cookbook/FSM.scala b/src/test/scala/cookbook/FSM.scala index 170d110f..f33bfee4 100644 --- a/src/test/scala/cookbook/FSM.scala +++ b/src/test/scala/cookbook/FSM.scala @@ -53,7 +53,7 @@ class DetectTwoOnesTester extends CookbookTester(10) { // Inputs and expected results val inputs: Vec[Bool] = VecInit(false.B, true.B, false.B, true.B, true.B, true.B, false.B, true.B, true.B, false.B) - val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) + val expected: Vec[Bool] = VecInit(false.B, false.B, false.B, false.B, false.B, true.B, true.B, false.B, false.B, true.B) // scalastyle:ignore line.size.limit dut.io.in := inputs(cycle) assert(dut.io.out === expected(cycle)) |