Split #974 into two PRs - scalastyle updates (#1037)

* Update style warnings now that subprojects are aggregated.
Use "scalastyle-test-config.xml" for scalastyle config in tests.
Enable "_" in method names and accept method names ending in "_=".
Re-sync scalastyle-test-config.xml with scalastyle-config.xml

* Remove bogus tests that crept in with git add

* Add missing import.

23 files changed, 147 insertions, 109 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index fa23ddaa..65939ef7 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -16,7 +16,7 @@ import chisel3.SourceInfoDoc
   * of) other Data objects.
   */
 sealed abstract class Aggregate extends Data {
-  private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) {
+  private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection) { // scalastyle:ignore cyclomatic.complexity line.size.limit
     binding = target
 
     val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection)
@@ -58,7 +58,7 @@ sealed abstract class Aggregate extends Data {
         }
         case _ =>
           val childWithDirections = getElements zip getElements.map(_.direction)
-          throw Binding.MixedDirectionAggregateException(s"Aggregate '$this' can't have elements that are both directioned and undirectioned: $childWithDirections")
+          throw Binding.MixedDirectionAggregateException(s"Aggregate '$this' can't have elements that are both directioned and undirectioned: $childWithDirections") // scalastyle:ignore line.size.limit
       }
     }
   }
@@ -111,17 +111,19 @@ trait VecFactory extends SourceInfoDoc {
   }
 
   /** Truncate an index to implement modulo-power-of-2 addressing. */
-  private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = {
+  private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt = { // scalastyle:ignore line.size.limit
+    // scalastyle:off if.brace
     val w = BigInt(n-1).bitLength
     if (n <= 1) 0.U
     else if (idx.width.known && idx.width.get <= w) idx
     else if (idx.width.known) idx(w-1,0)
     else (idx | 0.U(w.W))(w-1,0)
+    // scalastyle:on if.brace
   }
 }
 
 object Vec extends VecFactory
-
+// scalastyle:off line.size.limit
 /** A vector (array) of [[Data]] elements. Provides hardware versions of various
   * collection transformation functions found in software array implementations.
   *
@@ -148,6 +150,7 @@ object Vec extends VecFactory
   *  - when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined)
   *  - Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier
   */
+// scalastyle:on line.size.limit
 sealed class Vec[T <: Data] private[core] (gen: => T, val length: Int)
     extends Aggregate with VecLike[T] {
   override def toString: String = {
@@ -195,7 +198,7 @@ sealed class Vec[T <: Data] private[core] (gen: => T, val length: Int)
   }
 
   // TODO: eliminate once assign(Seq) isn't ambiguous with assign(Data) since Vec extends Seq and Data
-  def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this bulkConnect that.asInstanceOf[Data]
+  def <> (that: Vec[T])(implicit sourceInfo: SourceInfo, moduleCompileOptions: CompileOptions): Unit = this bulkConnect that.asInstanceOf[Data] // scalastyle:ignore line.size.limit
 
   /** Strong bulk connect, assigning elements in this Vec from elements in a Seq.
     *
@@ -258,9 +261,11 @@ sealed class Vec[T <: Data] private[core] (gen: => T, val length: Int)
     * Results in "Vec(elt0, elt1, ...)"
     */
   def toPrintable: Printable = {
+    // scalastyle:off if.brace
     val elts =
       if (length == 0) List.empty[Printable]
       else self flatMap (e => List(e.toPrintable, PString(", "))) dropRight 1
+    // scalastyle:on if.brace
     PString("Vec(") + Printables(elts) + PString(")")
   }
 }
@@ -332,7 +337,7 @@ object VecInit extends SourceInfoDoc {
   def tabulate[T <: Data](n: Int)(gen: (Int) => T): Vec[T] = macro VecTransform.tabulate
 
   /** @group SourceInfoTransformMacro */
-  def do_tabulate[T <: Data](n: Int)(gen: (Int) => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =
+  def do_tabulate[T <: Data](n: Int)(gen: (Int) => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Vec[T] =  // scalastyle:ignore line.size.limit
     apply((0 until n).map(i => gen(i)))
 }
 
@@ -494,11 +499,13 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio
 
   // Helper because Bundle elements are reversed before printing
   private[chisel3] def toPrintableHelper(elts: Seq[(String, Data)]): Printable = {
+    // scalastyle:off if.brace
     val xs =
       if (elts.isEmpty) List.empty[Printable] // special case because of dropRight below
       else elts flatMap { case (name, data) =>
              List(PString(s"$name -> "), data.toPrintable, PString(", "))
            } dropRight 1 // Remove trailing ", "
+    // scalastyle:on if.brace
     PString(s"$className(") + Printables(xs) + PString(")")
   }
   /** Default "pretty-print" implementation
@@ -612,6 +619,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
       }
     }
     ListMap(nameMap.toSeq sortWith { case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn)) }: _*)
+    // scalastyle:ignore method.length
   }
 
   /**
@@ -638,7 +646,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
   private val _containingModule: Option[BaseModule] = Builder.currentModule
   private val _containingBundles: Seq[Bundle] = Builder.updateBundleStack(this)
 
-  override def cloneType : this.type = {
+  override def cloneType : this.type = { // scalastyle:ignore cyclomatic.complexity method.length
     // This attempts to infer constructor and arguments to clone this Bundle subtype without
     // requiring the user explicitly overriding cloneType.
     import scala.language.existentials
@@ -718,7 +726,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
           Some(ctor.newInstance().asInstanceOf[this.type])
         case (argType :: Nil, Some((_, outerInstance))) =>
           if (outerInstance == null) {
-            Builder.deprecated(s"chisel3.1 autoclonetype failed, falling back to 3.0 behavior using null as the outer instance." +
+            Builder.deprecated(s"chisel3.1 autoclonetype failed, falling back to 3.0 behavior using null as the outer instance." + // scalastyle:ignore line.size.limit
                 s" Autoclonetype failure reason: ${outerClassError.get}",
                 Some(s"$clazz"))
             Some(ctor.newInstance(outerInstance).asInstanceOf[this.type])
@@ -745,7 +753,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
     // Get constructor parameters and accessible fields
     val classSymbol = classSymbolOption.getOrElse(autoClonetypeError(s"scala reflection failed." +
         " This is known to occur with inner classes on anonymous outer classes." +
-        " In those cases, autoclonetype only works with no-argument constructors, or you can define a custom cloneType."))
+        " In those cases, autoclonetype only works with no-argument constructors, or you can define a custom cloneType.")) // scalastyle:ignore line.size.limit
 
     val decls = classSymbol.typeSignature.decls
     val ctors = decls.collect { case meth: MethodSymbol if meth.isConstructor => meth }
@@ -795,8 +803,10 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
     val accessorsName = accessors.filter(_.isStable).map(_.name.toString)
     val paramsDiff = ctorParamsNames.toSet -- accessorsName.toSet
     if (!paramsDiff.isEmpty) {
+      // scalastyle:off line.size.limit
       autoClonetypeError(s"constructor has parameters (${paramsDiff.toList.sorted.mkString(", ")}) that are not both immutable and accessible." +
           " Either make all parameters immutable and accessible (vals) so cloneType can be inferred, or define a custom cloneType method.")
+      // scalastyle:on line.size.limit
     }
 
     // Get all the argument values
@@ -813,8 +823,10 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
       case (paramName, paramVal: Data) if paramVal.topBindingOpt.isDefined => paramName
     }
     if (boundDataParamNames.nonEmpty) {
+      // scalastyle:off line.size.limit
       autoClonetypeError(s"constructor parameters (${boundDataParamNames.sorted.mkString(", ")}) have values that are hardware types, which is likely to cause subtle errors." +
           " Use chisel types instead: use the value before it is turned to a hardware type (with Wire(...), Reg(...), etc) or use chiselTypeOf(...) to extract the chisel type.")
+      // scalastyle:on line.size.limit
     }
 
     // Clone unbound parameters in case they are being used as bundle fields.
@@ -833,9 +845,11 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
     clone._outerInst = this._outerInst
 
     if (!clone.typeEquivalent(this)) {
+      // scalastyle:off line.size.limit
       autoClonetypeError(s"Automatically cloned $clone not type-equivalent to base $this." +
           " Constructor argument values were inferred: ensure that variable names are consistent and have the same value throughout the constructor chain," +
           " and that the constructor is deterministic.")
+      // scalastyle:on line.size.limit
     }
 
     clone
@@ -848,4 +862,6 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
     *   the fields in the order they were defined
     */
   override def toPrintable: Printable = toPrintableHelper(elements.toList.reverse)
+  // scalastyle:off method.length
 }
+// scalastyle:off file.size.limit
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
index cfee67cb..93a02139 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala
@@ -19,7 +19,7 @@ trait ChiselAnnotation {
 }
 object ChiselAnnotation {
   @deprecated("Write a custom ChiselAnnotation subclass instead", "3.1")
-  def apply(component: InstanceId, transformClass: Class[_ <: Transform], value: String) =
+  def apply(component: InstanceId, transformClass: Class[_ <: Transform], value: String): ChiselLegacyAnnotation =
     ChiselLegacyAnnotation(component, transformClass, value)
   @deprecated("Write a custom ChiselAnnotation subclass instead", "3.1")
   def unapply(anno: ChiselAnnotation): Option[(InstanceId, Class[_ <: Transform], String)] =
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
index 77db3692..054222c3 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Assert.scala
@@ -32,10 +32,10 @@ object assert { // scalastyle:ignore object.name
     * that
     */
   // Macros currently can't take default arguments, so we need two functions to emulate defaults.
-  def apply(cond: Bool, message: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = macro apply_impl_msg_data
+  def apply(cond: Bool, message: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = macro apply_impl_msg_data // scalastyle:ignore line.size.limit
   def apply(cond: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = macro apply_impl
 
-  def apply_impl_msg_data(c: Context)(cond: c.Tree, message: c.Tree, data: c.Tree*)(sourceInfo: c.Tree, compileOptions: c.Tree): c.Tree = {
+  def apply_impl_msg_data(c: Context)(cond: c.Tree, message: c.Tree, data: c.Tree*)(sourceInfo: c.Tree, compileOptions: c.Tree): c.Tree = { // scalastyle:ignore line.size.limit
     import c.universe._
     val p = c.enclosingPosition
     val condStr = s"${p.source.file.name}:${p.line} ${p.lineContent.trim}"
@@ -51,7 +51,7 @@ object assert { // scalastyle:ignore object.name
     q"$apply_impl_do($cond, $condStr, _root_.scala.None)($sourceInfo, $compileOptions)"
   }
 
-  def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) {
+  def apply_impl_do(cond: Bool, line: String, message: Option[String], data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions) { // scalastyle:ignore line.size.limit
     val escLine = line.replaceAll("%", "%%")
     when (!(cond || Module.reset.asBool)) {
       val fmt = message match {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Attach.scala b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala
index 8cb58f1c..5fb89b18 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Attach.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala
@@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.{SourceInfo}
 object attach {  // scalastyle:ignore object.name
   // Exceptions that can be generated by attach
   case class AttachException(message: String) extends ChiselException(message)
-  def ConditionalAttachException =
+  def ConditionalAttachException: AttachException = // scalastyle:ignore method.name
     AttachException(": Conditional attach is not allowed!")
 
   // Actual implementation
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 897ccacf..b1f9bcb5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -23,6 +23,7 @@ import chisel3.internal.sourceinfo._
 */
 
 object BiConnect {
+  // scalastyle:off method.name public.methods.have.type
   // These are all the possible exceptions that can be thrown.
   case class BiConnectException(message: String) extends ChiselException(message)
   // These are from element-level connection
@@ -47,7 +48,7 @@ object BiConnect {
     BiConnectException(sourceInfo.makeMessage(": Analog previously bulk connected at " + _))
   def DontCareCantBeSink =
     BiConnectException(": DontCare cannot be a connection sink (LHS)")
-
+  // scalastyle:on method.name public.methods.have.type
 
   /** This function is what recursively tries to connect a left and right together
   *
@@ -55,7 +56,7 @@ object BiConnect {
   * during the recursive decent and then rethrow them with extra information added.
   * This gives the user a 'path' to where in the connections things went wrong.
   */
-  def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: RawModule): Unit = {
+  def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: RawModule): Unit = { // scalastyle:ignore line.size.limit cyclomatic.complexity method.length
     (left, right) match {
       // Handle element case (root case)
       case (left_a: Analog, right_a: Analog) =>
@@ -207,7 +208,7 @@ object BiConnect {
 
   // This function checks if element-level connection operation allowed.
   // Then it either issues it or throws the appropriate exception.
-  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: RawModule): Unit = {
+  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: RawModule): Unit = { // scalastyle:ignore line.size.limit cyclomatic.complexity method.length
     import BindingDirection.{Internal, Input, Output} // Using extensively so import these
     // If left or right have no location, assume in context module
     // This can occur if one of them is a literal, unbound will error previously
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
index 4c352bc6..55e6bcf9 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 package chisel3.core
 
 import chisel3.internal.ChiselException
@@ -23,7 +25,7 @@ object Binding {
 /** Requires that a node is hardware ("bound")
   */
 object requireIsHardware {
-  def apply(node: Data, msg: String = "") = {
+  def apply(node: Data, msg: String = ""): Unit = {
     node._parent match {  // Compatibility layer hack
       case Some(x: BaseModule) => x._compatAutoWrapPorts
       case _ =>
@@ -39,7 +41,7 @@ object requireIsHardware {
 /** Requires that a node is a chisel type (not hardware, "unbound")
   */
 object requireIsChiselType {
-  def apply(node: Data, msg: String = "") = if (node.topBindingOpt.isDefined) {
+  def apply(node: Data, msg: String = ""): Unit = if (node.topBindingOpt.isDefined) {
     val prefix = if (msg.nonEmpty) s"$msg " else ""
     throw Binding.ExpectedChiselTypeException(s"$prefix'$node' must be a Chisel type, not hardware")
   }
@@ -60,7 +62,7 @@ object BindingDirection {
 
   /** Determine the BindingDirection of an Element given its top binding and resolved direction.
     */
-  def from(binding: TopBinding, direction: ActualDirection) = {
+  def from(binding: TopBinding, direction: ActualDirection): BindingDirection = {
     binding match {
       case PortBinding(_) => direction match {
         case ActualDirection.Output => Output
@@ -82,13 +84,13 @@ sealed trait TopBinding extends Binding
 // Constrained-ness refers to whether 'bound by Module boundaries'
 // An unconstrained binding, like a literal, can be read by everyone
 sealed trait UnconstrainedBinding extends TopBinding {
-  def location = None
+  def location: Option[BaseModule] = None
 }
 // A constrained binding can only be read/written by specific modules
 // Location will track where this Module is
 sealed trait ConstrainedBinding extends TopBinding {
   def enclosure: BaseModule
-  def location = Some(enclosure)
+  def location: Option[BaseModule] = Some(enclosure)
 }
 
 // A binding representing a data that cannot be (re)assigned to.
@@ -103,7 +105,7 @@ case class RegBinding(enclosure: RawModule) extends ConstrainedBinding
 case class WireBinding(enclosure: RawModule) extends ConstrainedBinding
 
 case class ChildBinding(parent: Data) extends Binding {
-  def location = parent.topBinding.location
+  def location: Option[BaseModule] = parent.topBinding.location
 }
 // A DontCare element has a specific Binding, somewhat like a literal.
 // It is a source (RHS). It may only be connected/applied to sinks.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index db2562a5..7270d92b 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -12,7 +12,7 @@ import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, SourceInfo
   UIntTransform}
 import chisel3.internal.firrtl.PrimOp._
 
-//scalastyle:off method.name
+// scalastyle:off method.name line.size.limit file.size.limit
 
 /** Element is a leaf data type: it cannot contain other [[Data]] objects. Example uses are for representing primitive
   * data types, like integers and bits.
@@ -1761,7 +1761,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
   private[core] override def typeEquivalent(that: Data): Boolean =
     that.isInstanceOf[Analog] && this.width == that.width
 
-  override def litOption = None
+  override def litOption: Option[BigInt] = None
 
   def cloneType: this.type = new Analog(width).asInstanceOf[this.type]
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index 57acd7b3..e8dc2bfe 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -123,11 +123,11 @@ abstract class ExtModule(val params: Map[String, Param] = Map.empty[String, Para
   * }}}
   * @note The parameters API is experimental and may change
   */
-abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param])(implicit compileOptions: CompileOptions) extends BaseBlackBox {
+abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param])(implicit compileOptions: CompileOptions) extends BaseBlackBox { // scalastyle:ignore line.size.limit
   def io: Record
 
   // Allow access to bindings from the compatibility package
-  protected def _compatIoPortBound() = portsContains(io)
+  protected def _compatIoPortBound() = portsContains(io) // scalastyle:ignore method.name
 
   private[core] override def generateComponent(): Component = {
     _compatAutoWrapPorts()  // pre-IO(...) compatibility hack
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Clock.scala b/chiselFrontend/src/main/scala/chisel3/core/Clock.scala
index 1bc2260c..364ac5aa 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Clock.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Clock.scala
@@ -20,17 +20,17 @@ sealed class Clock(private[chisel3] val width: Width = Width(1)) extends Element
   private[core] def typeEquivalent(that: Data): Boolean =
     this.getClass == that.getClass
 
-  override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match {
+  override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match { // scalastyle:ignore line.size.limit
     case _: Clock => super.connect(that)(sourceInfo, connectCompileOptions)
     case _ => super.badConnect(that)(sourceInfo)
   }
 
-  override def litOption = None
+  override def litOption: Option[BigInt] = None
 
   /** Not really supported */
   def toPrintable: Printable = PString("CLOCK")
 
-  override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref))
+  override def do_asUInt(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): UInt = pushOp(DefPrim(sourceInfo, UInt(this.width), AsUIntOp, ref)) // scalastyle:ignore line.size.limit
   private[core] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
       compileOptions: CompileOptions): Unit = {
     this := that
diff --git a/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala
index e22519d9..a2f94e51 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/CompileOptions.scala
@@ -35,21 +35,21 @@ object CompileOptions {
 
 object ExplicitCompileOptions {
   case class CompileOptionsClass (
-                             // Should Record connections require a strict match of fields.
-                             // If true and the same fields aren't present in both source and sink, a MissingFieldException,
-                             // MissingLeftFieldException, or MissingRightFieldException will be thrown.
-                             val connectFieldsMustMatch: Boolean,
-                             // When creating an object that takes a type argument, the argument must be unbound (a pure type).
-                             val declaredTypeMustBeUnbound: Boolean,
-                             // If a connection operator fails, don't try the connection with the operands (source and sink) reversed.
-                             val dontTryConnectionsSwapped: Boolean,
-                             // If connection directionality is not explicit, do not use heuristics to attempt to determine it.
-                             val dontAssumeDirectionality: Boolean,
-                             // Check that referenced Data have actually been declared.
-                             val checkSynthesizable: Boolean,
-                             // Require an explicit DontCare assignment to generate a firrtl DefInvalid
-                             val explicitInvalidate: Boolean
-                           ) extends CompileOptions
+    // Should Record connections require a strict match of fields.
+    // If true and the same fields aren't present in both source and sink, a MissingFieldException,
+    // MissingLeftFieldException, or MissingRightFieldException will be thrown.
+    val connectFieldsMustMatch: Boolean,
+    // When creating an object that takes a type argument, the argument must be unbound (a pure type).
+    val declaredTypeMustBeUnbound: Boolean,
+    // If a connection operator fails, don't try the connection with the operands (source and sink) reversed.
+    val dontTryConnectionsSwapped: Boolean,
+    // If connection directionality is not explicit, do not use heuristics to attempt to determine it.
+    val dontAssumeDirectionality: Boolean,
+    // Check that referenced Data have actually been declared.
+    val checkSynthesizable: Boolean,
+    // Require an explicit DontCare assignment to generate a firrtl DefInvalid
+    val explicitInvalidate: Boolean
+  ) extends CompileOptions
 
   // Collection of "not strict" connection compile options.
   // These provide compatibility with existing code.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 06fb27cc..45afed94 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -28,7 +28,7 @@ object SpecifiedDirection {
     */
   case object Flip extends SpecifiedDirection
 
-  def flip(dir: SpecifiedDirection) = dir match {
+  def flip(dir: SpecifiedDirection): SpecifiedDirection = dir match {
     case Unspecified => Flip
     case Flip => Unspecified
     case Output => Input
@@ -38,7 +38,7 @@ object SpecifiedDirection {
   /** Returns the effective SpecifiedDirection of this node given the parent's effective SpecifiedDirection
     * and the user-specified SpecifiedDirection of this node.
     */
-  def fromParent(parentDirection: SpecifiedDirection, thisDirection: SpecifiedDirection) =
+  def fromParent(parentDirection: SpecifiedDirection, thisDirection: SpecifiedDirection): SpecifiedDirection =
     (parentDirection, thisDirection) match {
       case (SpecifiedDirection.Output, _) => SpecifiedDirection.Output
       case (SpecifiedDirection.Input, _) => SpecifiedDirection.Input
@@ -105,8 +105,8 @@ object DataMirror {
   }
 
   // Internal reflection-style APIs, subject to change and removal whenever.
-  object internal {
-    def isSynthesizable(target: Data) = target.topBindingOpt.isDefined
+  object internal { // scalastyle:ignore object.name
+    def isSynthesizable(target: Data): Boolean = target.topBindingOpt.isDefined
     // For those odd cases where you need to care about object reference and uniqueness
     def chiselTypeClone[T<:Data](target: Data): T = {
       target.cloneTypeFull.asInstanceOf[T]
@@ -222,7 +222,7 @@ object Flipped {
   * @groupdesc Connect Utilities for connecting hardware components
   * @define coll data
   */
-abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
+abstract class Data extends HasId with NamedComponent with SourceInfoDoc { // scalastyle:ignore number.of.methods
   // This is a bad API that punches through object boundaries.
   @deprecated("pending removal once all instances replaced", "chisel3")
   private[chisel3] def flatten: IndexedSeq[Element] = {
@@ -252,7 +252,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
     * the compatibility layer where, at the elements, Flip is Input and unspecified is Output.
     * DO NOT USE OUTSIDE THIS PURPOSE. THIS OPERATION IS DANGEROUS!
     */
-  private[core] def _assignCompatibilityExplicitDirection: Unit = {
+  private[core] def _assignCompatibilityExplicitDirection: Unit = { // scalastyle:off method.name
     (this, _specifiedDirection) match {
       case (_: Analog, _) => // nothing to do
       case (_, SpecifiedDirection.Unspecified) => _specifiedDirection = SpecifiedDirection.Output
@@ -332,7 +332,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
 
   private[core] def badConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
     throwException(s"cannot connect ${this} and ${that}")
-  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = {
+  private[chisel3] def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit
     if (connectCompileOptions.checkSynthesizable) {
       requireIsHardware(this, "data to be connected")
       requireIsHardware(that, "data to be connected")
@@ -352,7 +352,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
       this legacyConnect that
     }
   }
-  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = {
+  private[chisel3] def bulkConnect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit
     if (connectCompileOptions.checkSynthesizable) {
       requireIsHardware(this, s"data to be bulk-connected")
       requireIsHardware(that, s"data to be bulk-connected")
@@ -384,7 +384,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
   private[chisel3] def lref: Node = {
     requireIsHardware(this)
     topBindingOpt match {
-      case Some(binding: ReadOnlyBinding) => throwException(s"internal error: attempted to generate LHS ref to ReadOnlyBinding $binding")
+      case Some(binding: ReadOnlyBinding) => throwException(s"internal error: attempted to generate LHS ref to ReadOnlyBinding $binding") // scalastyle:ignore line.size.limit
       case Some(binding: TopBinding) => Node(this)
       case opt => throwException(s"internal error: unknown binding $opt in generating LHS ref")
     }
@@ -432,7 +432,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
     * @param that the $coll to connect to
     * @group Connect
     */
-  final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions)
+  final def := (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.connect(that)(sourceInfo, connectionCompileOptions) // scalastyle:ignore line.size.limit
 
   /** Connect this $coll to that $coll bi-directionally and element-wise.
     *
@@ -441,7 +441,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc {
     * @param that the $coll to connect to
     * @group Connect
     */
-  final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions)
+  final def <> (that: Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit = this.bulkConnect(that)(sourceInfo, connectionCompileOptions) // scalastyle:ignore line.size.limit
 
   @chiselRuntimeDeprecated
   @deprecated("litArg is deprecated, use litOption or litTo*Option", "chisel3.2")
@@ -626,7 +626,7 @@ object Wire extends WireFactory
   */
 object WireDefault {
 
-  private def applyImpl[T <: Data](t: T, init: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
+  private def applyImpl[T <: Data](t: T, init: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { // scalastyle:ignore line.size.limit
     implicit val noSourceInfo = UnlocatableSourceInfo
     val x = Wire(t)
     requireIsHardware(init, "wire initializer")
@@ -641,7 +641,7 @@ object WireDefault {
     *   @note This is really just a specialized form of `apply[T <: Data](t: T, init: T): T` with [[DontCare]]
     *   as `init`
     */
-  def apply[T <: Data](t: T, init: DontCare.type)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
+  def apply[T <: Data](t: T, init: DontCare.type)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = { // scalastyle:ignore line.size.limit
     applyImpl(t, init)
   }
 
@@ -678,19 +678,19 @@ object DontCare extends Element {
   private[chisel3] override val width: Width = UnknownWidth()
 
   bind(DontCareBinding(), SpecifiedDirection.Output)
-  override def cloneType = DontCare
+  override def cloneType: this.type = DontCare
 
   override def toString: String = "DontCare()"
 
-  override def litOption = None
+  override def litOption: Option[BigInt] = None
 
   def toPrintable: Printable = PString("DONTCARE")
 
-  private[core] def connectFromBits(that: chisel3.core.Bits)(implicit sourceInfo:  SourceInfo, compileOptions: CompileOptions): Unit = {
+  private[core] def connectFromBits(that: chisel3.core.Bits)(implicit sourceInfo:  SourceInfo, compileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit
     Builder.error("connectFromBits: DontCare cannot be a connection sink (LHS)")
   }
 
-  def do_asUInt(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): chisel3.core.UInt = {
+  def do_asUInt(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): chisel3.core.UInt = { // scalastyle:ignore line.size.limit
     Builder.error("DontCare does not have a UInt representation")
     0.U
   }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index 09e30fec..f9211ee7 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -11,6 +11,7 @@ import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform, Unlocatable
 import chisel3.SourceInfoDoc
 
 object Mem {
+  // scalastyle:off line.size.limit
   @chiselRuntimeDeprecated
   @deprecated("Mem argument order should be size, t; this will be removed by the official release", "chisel3")
   def apply[T <: Data](t: T, size: Int)(implicit compileOptions: CompileOptions): Mem[T] = do_apply(size, t)(UnlocatableSourceInfo, compileOptions)
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 751d5401..0a5e522f 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -204,14 +204,14 @@ abstract class BaseModule extends HasId {
   /** Desired name of this module. Override this to give this module a custom, perhaps parametric,
     * name.
     */
-  def desiredName = this.getClass.getName.split('.').last
+  def desiredName:String = this.getClass.getName.split('.').last
 
   /** Legalized name of this module. */
   final lazy val name = try {
     Builder.globalNamespace.name(desiredName)
   } catch {
     case e: NullPointerException => throwException(
-      s"Error: desiredName of ${this.getClass.getName} is null. Did you evaluate 'name' before all values needed by desiredName were available?", e)
+      s"Error: desiredName of ${this.getClass.getName} is null. Did you evaluate 'name' before all values needed by desiredName were available?", e) // scalastyle:ignore line.size.limit
     case t: Throwable => throw t
   }
 
@@ -272,7 +272,7 @@ abstract class BaseModule extends HasId {
     *
     * TODO: remove this, perhaps by removing Bindings checks in compatibility mode.
     */
-  def _compatAutoWrapPorts() {}
+  def _compatAutoWrapPorts() {} // scalastyle:ignore method.name
 
   //
   // BaseModule User API functions
@@ -285,7 +285,7 @@ abstract class BaseModule extends HasId {
   /** Chisel2 code didn't require the IO(...) wrapper and would assign a Chisel type directly to
     * io, then do operations on it. This binds a Chisel type in-place (mutably) as an IO.
     */
-  protected def _bindIoInPlace(iodef: Data): Unit = {
+  protected def _bindIoInPlace(iodef: Data): Unit = { // scalastyle:ignore method.name
     // Compatibility code: Chisel2 did not require explicit direction on nodes
     // (unspecified treated as output, and flip on nothing was input).
     // This sets assigns the explicit directions required by newer semantics on
@@ -334,7 +334,7 @@ abstract class BaseModule extends HasId {
    * TODO(twigg): Specifically walk the Data definition to call out which nodes
    * are problematic.
    */
-  protected def IO[T<:Data](iodef: T): T = chisel3.core.IO.apply(iodef)
+  protected def IO[T<:Data](iodef: T): T = chisel3.core.IO.apply(iodef) // scalastyle:ignore method.name
 
   //
   // Internal Functions
@@ -344,7 +344,7 @@ abstract class BaseModule extends HasId {
   private[chisel3] var _component: Option[Component] = None
 
   /** Signal name (for simulation). */
-  override def instanceName =
+  override def instanceName: String =
     if (_parent == None) name else _component match {
       case None => getRef.name
       case Some(c) => getRef fullName c
diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
index 0773c7a2..6a4ae9bf 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala
@@ -33,6 +33,7 @@ import chisel3.internal.sourceinfo.SourceInfo
 */
 
 object MonoConnect {
+  // scalastyle:off method.name public.methods.have.type
   // These are all the possible exceptions that can be thrown.
   case class MonoConnectException(message: String) extends ChiselException(message)
   // These are from element-level connection
@@ -51,6 +52,7 @@ object MonoConnect {
     MonoConnectException(s": Sink ($sink) and Source ($source) have different types.")
   def DontCareCantBeSink =
     MonoConnectException(": DontCare cannot be a connection sink (LHS)")
+  // scalastyle:on method.name public.methods.have.type
 
   /** This function is what recursively tries to connect a sink and source together
   *
@@ -58,8 +60,7 @@ object MonoConnect {
   * during the recursive decent and then rethrow them with extra information added.
   * This gives the user a 'path' to where in the connections things went wrong.
   */
-  //scalastyle:off cyclomatic.complexity method.length
-  def connect(
+  def connect(  //scalastyle:off cyclomatic.complexity method.length
       sourceInfo: SourceInfo,
       connectCompileOptions: CompileOptions,
       sink: Data,
@@ -157,7 +158,7 @@ object MonoConnect {
 
   // This function checks if element-level connection operation allowed.
   // Then it either issues it or throws the appropriate exception.
-  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: RawModule): Unit = {
+  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: RawModule): Unit = { // scalastyle:ignore line.size.limit
     import BindingDirection.{Internal, Input, Output} // Using extensively so import these
     // If source has no location, assume in context module
     // This can occur if is a literal, unbound will error previously
@@ -196,7 +197,7 @@ object MonoConnect {
             throw UnreadableSourceException
           }
         }
-        case (Input,        Output) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink)
+        case (Input,        Output) if (!(connectCompileOptions.dontTryConnectionsSwapped)) => issueConnect(source, sink) // scalastyle:ignore line.size.limit
         case (Input,        _)    => throw UnwritableSinkException
       }
     }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala
index 7b3d8d4f..c724f682 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala
@@ -54,14 +54,14 @@ sealed abstract class Printable {
     */
   def unpack(ctx: Component): (String, Iterable[String])
   /** Allow for appending Printables like Strings */
-  final def +(that: Printable) = Printables(List(this, that))
+  final def +(that: Printable): Printables = Printables(List(this, that))
   /** Allow for appending Strings to Printables */
-  final def +(that: String) = Printables(List(this, PString(that)))
+  final def +(that: String): Printables = Printables(List(this, PString(that)))
 }
 object Printable {
   /** Pack standard printf fmt, args* style into Printable
     */
-  def pack(fmt: String, data: Data*): Printable = {
+  def pack(fmt: String, data: Data*): Printable = { // scalastyle:ignore method.length
     val args = data.toIterator
 
     // Error handling
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
index 53b62bc8..5c2f89e9 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Printf.scala
@@ -91,10 +91,10 @@ object printf { // scalastyle:ignore object.name
     }
   }
 
-  private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = {
+  private[chisel3] def printfWithoutReset(pable: Printable)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = { // scalastyle:ignore line.size.limit
     val clock = Builder.forcedClock
     pushCommand(Printf(sourceInfo, clock.ref, pable))
   }
-  private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit =
+  private[chisel3] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit = // scalastyle:ignore line.size.limit
     printfWithoutReset(Printable.pack(fmt, data:_*))
 }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala
index 1a9911e6..00e78295 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala
@@ -56,7 +56,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
   }
 
 
-  private[core] override def generateComponent(): Component = {
+  private[core] override def generateComponent(): Component = { // scalastyle:ignore cyclomatic.complexity
     require(!_closed, "Can't generate module more than once")
     _closed = true
 
@@ -164,22 +164,22 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions)
 
   @chiselRuntimeDeprecated
   @deprecated("Module constructor with override _clock deprecated, use withClock", "chisel3")
-  def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions)
+  def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions) // scalastyle:ignore line.size.limit
 
   @chiselRuntimeDeprecated
   @deprecated("Module constructor with override _reset deprecated, use withReset", "chisel3")
-  def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)  = this(None, Option(_reset))(moduleCompileOptions)
+  def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)  = this(None, Option(_reset))(moduleCompileOptions) // scalastyle:ignore line.size.limit
 
   @chiselRuntimeDeprecated
   @deprecated("Module constructor with override _clock, _reset deprecated, use withClockAndReset", "chisel3")
-  def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions)
+  def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions) // scalastyle:ignore line.size.limit
 
   // IO for this Module. At the Scala level (pre-FIRRTL transformations),
   // connections in and out of a Module may only go through `io` elements.
   def io: Record
 
   // Allow access to bindings from the compatibility package
-  protected def _compatIoPortBound() = portsContains(io)
+  protected def _compatIoPortBound() = portsContains(io)// scalastyle:ignore method.name
 
   protected override def nameIds(rootClass: Class[_]): HashMap[HasId, String] = {
     val names = super.nameIds(rootClass)
@@ -207,7 +207,7 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions)
     // Restrict IO to just io, clock, and reset
     require(io != null, "Module must have io")
     require(portsContains(io), "Module must have io wrapped in IO(...)")
-    require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO")
+    require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") // scalastyle:ignore line.size.limit
     require(portsSize == 3, "Module must only have io, clock, and reset as IO")
 
     super.generateComponent()
diff --git a/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala b/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala
index 8feb0541..f9414901 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/StrongEnum.scala
@@ -16,11 +16,11 @@ import firrtl.annotations._
 
 object EnumAnnotations {
   case class EnumComponentAnnotation(target: Named, enumTypeName: String) extends SingleTargetAnnotation[Named] {
-    def duplicate(n: Named) = this.copy(target = n)
+    def duplicate(n: Named): EnumComponentAnnotation = this.copy(target = n)
   }
 
   case class EnumComponentChiselAnnotation(target: InstanceId, enumTypeName: String) extends ChiselAnnotation {
-    def toFirrtl = EnumComponentAnnotation(target.toNamed, enumTypeName)
+    def toFirrtl: EnumComponentAnnotation = EnumComponentAnnotation(target.toNamed, enumTypeName)
   }
 
   case class EnumDefAnnotation(enumTypeName: String, definition: Map[String, BigInt]) extends NoTargetAnnotation
@@ -52,8 +52,9 @@ abstract class EnumType(private val factory: EnumFactory, selfAnnotating: Boolea
     requireIsHardware(this, "bits operated on")
     requireIsHardware(other, "bits operated on")
 
-    if(!this.typeEquivalent(other))
+    if(!this.typeEquivalent(other)) {
       throwException(s"Enum types are not equivalent: ${this.enumTypeName}, ${other.enumTypeName}")
+    }
 
     pushOp(DefPrim(sourceInfo, Bool(), op, this.ref, other.ref))
   }
@@ -75,12 +76,14 @@ abstract class EnumType(private val factory: EnumFactory, selfAnnotating: Boolea
   final def > (that: EnumType): Bool = macro SourceInfoTransform.thatArg
   final def >= (that: EnumType): Bool = macro SourceInfoTransform.thatArg
 
+  // scalastyle:off line.size.limit method.name
   def do_=== (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, EqualOp, that)
   def do_=/= (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, NotEqualOp, that)
   def do_< (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, LessOp, that)
   def do_> (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, GreaterOp, that)
   def do_<= (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, LessEqOp, that)
   def do_>= (that: EnumType)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = compop(sourceInfo, GreaterEqOp, that)
+  // scalastyle:on line.size.limit method.name
 
   override def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt =
     pushOp(DefPrim(sourceInfo, UInt(width), AsUIntOp, ref))
@@ -99,10 +102,11 @@ abstract class EnumType(private val factory: EnumFactory, selfAnnotating: Boolea
     if (litOption.isDefined) {
       val index = factory.all.indexOf(this)
 
-      if (index < factory.all.length-1)
-        factory.all(index+1).asInstanceOf[this.type]
-      else
+      if (index < factory.all.length-1) {
+        factory.all(index + 1).asInstanceOf[this.type]
+      } else {
         factory.all.head.asInstanceOf[this.type]
+      }
     } else {
       val enums_with_nexts = factory.all zip (factory.all.tail :+ factory.all.head)
       val next_enum = SeqUtils.priorityMux(enums_with_nexts.map { case (e,n) => (this === e, n) } )
@@ -168,8 +172,8 @@ abstract class EnumFactory {
     enum_records.find(_.inst.litValue() == id).map(_.name)
   }
 
-  protected def Value: Type = macro EnumMacros.ValImpl
-  protected def Value(id: UInt): Type = macro EnumMacros.ValCustomImpl
+  protected def Value: Type = macro EnumMacros.ValImpl // scalastyle:off method.name
+  protected def Value(id: UInt): Type = macro EnumMacros.ValCustomImpl // scalastyle:off method.name
 
   protected def do_Value(names: Seq[String]): Type = {
     val result = new Type
@@ -189,10 +193,12 @@ abstract class EnumFactory {
   protected def do_Value(names: Seq[String], id: UInt): Type = {
     // TODO: These throw ExceptionInInitializerError which can be confusing to the user. Get rid of the error, and just
     // throw an exception
-    if (id.litOption.isEmpty)
+    if (id.litOption.isEmpty) {
       throwException(s"$enumTypeName defined with a non-literal type")
-    if (id.litValue() < this.id)
+    }
+    if (id.litValue() < this.id) {
       throwException(s"Enums must be strictly increasing: $enumTypeName")
+    }
 
     this.id = id.litValue()
     do_Value(names)
@@ -201,6 +207,7 @@ abstract class EnumFactory {
   def apply(): Type = new Type
 
   def apply(n: UInt)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Type = {
+    // scalastyle:off line.size.limit
     if (n.litOption.isDefined) {
       val result = enumInstances.find(_.litValue == n.litValue)
 
@@ -223,17 +230,18 @@ abstract class EnumFactory {
       result
     }
   }
+  // scalastyle:on line.size.limit
 }
 
 
 private[core] object EnumMacros {
-  def ValImpl(c: Context) : c.Tree = {
+  def ValImpl(c: Context) : c.Tree = { // scalastyle:off method.name
     import c.universe._
     val names = getNames(c)
     q"""this.do_Value(Seq(..$names))"""
   }
 
-  def ValCustomImpl(c: Context)(id: c.Expr[UInt]) = {
+  def ValCustomImpl(c: Context)(id: c.Expr[UInt]): c.universe.Tree = { // scalastyle:off method.name
     import c.universe._
     val names = getNames(c)
     q"""this.do_Value(Seq(..$names), $id)"""
@@ -249,8 +257,9 @@ private[core] object EnumMacros {
         if rhs.pos == c.macroApplication.pos => name.decoded
     }
 
-    if (names.isEmpty)
+    if (names.isEmpty) {
       c.abort(c.enclosingPosition, "Value cannot be called without assigning to an enum")
+    }
 
     names
   }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala
index fb246e1b..78fc0fc5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/When.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala
@@ -28,11 +28,11 @@ object when {  // scalastyle:ignore object.name
     * }}}
     */
 
-  def apply(cond: => Bool)(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = {
+  def apply(cond: => Bool)(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { // scalastyle:ignore line.size.limit
     new WhenContext(sourceInfo, Some(() => cond), block)
   }
 }
- 
+
 /**  A WhenContext may represent a when, and elsewhen, or an
   *  otherwise. Since FIRRTL does not have an "elsif" statement,
   *  alternatives must be mapped to nested if-else statements inside
@@ -51,8 +51,8 @@ final class WhenContext(sourceInfo: SourceInfo, cond: Option[() => Bool], block:
     * declaration and assignment of the Bool node of the predicate in
     * the correct place.
     */
-  def elsewhen (elseCond: => Bool)(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = {
-    new WhenContext(sourceInfo, Some(() => elseCond), block, firrtlDepth+1)
+  def elsewhen (elseCond: => Bool)(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): WhenContext = { // scalastyle:ignore line.size.limit
+    new WhenContext(sourceInfo, Some(() => elseCond), block, firrtlDepth + 1)
   }
 
   /** This block of logic gets executed only if the above conditions
@@ -63,10 +63,10 @@ final class WhenContext(sourceInfo: SourceInfo, cond: Option[() => Bool], block:
     * place.
     */
   def otherwise(block: => Unit)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit =
-    new WhenContext(sourceInfo, None, block, firrtlDepth+1)
+    new WhenContext(sourceInfo, None, block, firrtlDepth + 1)
 
   /*
-   * 
+   *
    */
   if (firrtlDepth > 0) { pushCommand(AltBegin(sourceInfo)) }
   cond.foreach( c => pushCommand(WhenBegin(sourceInfo, c().ref)) )
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index cd75a8a0..46db337b 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -26,7 +26,7 @@ package chisel3 {
     implicit class fromBigIntToLiteral(bigint: BigInt) {
       /** Int to Bool conversion, allowing compact syntax like 1.B and 0.B
        */
-      def B: Bool = bigint match {
+      def B: Bool = bigint match { // scalastyle:ignore method.name
         case bigint if bigint == 0 => Bool.Lit(false)
         case bigint if bigint == 1 => Bool.Lit(true)
         case bigint => Builder.error(s"Cannot convert $bigint to Bool, must be 0 or 1"); Bool.Lit(false)
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index f0bb5605..dcf5dbde 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -146,8 +146,11 @@ private[chisel3] trait HasId extends InstanceId {
   private[chisel3] def getPublicFields(rootClass: Class[_]): Seq[java.lang.reflect.Method] = {
     // Suggest names to nodes using runtime reflection
     def getValNames(c: Class[_]): Set[String] = {
-      if (c == rootClass) Set()
-      else getValNames(c.getSuperclass) ++ c.getDeclaredFields.map(_.getName)
+      if (c == rootClass) {
+        Set()
+      } else {
+        getValNames(c.getSuperclass) ++ c.getDeclaredFields.map(_.getName)
+      }
     }
     val valNames = getValNames(this.getClass)
     def isPublicVal(m: java.lang.reflect.Method) =
@@ -225,7 +228,7 @@ private[chisel3] object Builder {
   def forcedUserModule: RawModule = currentModule match {
     case Some(module: RawModule) => module
     case _ => throwException(
-      "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox."
+      "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." // scalastyle:ignore line.size.limit
       // A bare api call is, e.g. calling Wire() from the scala console).
     )
   }
@@ -346,5 +349,5 @@ private[chisel3] object Builder {
   * objects.
   */
 object DynamicNamingStack {
-  def apply() = Builder.namingStack
+  def apply(): internal.naming.NamingStack = Builder.namingStack
 }
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
index 07f4db73..59f32542 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
@@ -34,7 +34,7 @@ class ChiselException(message: String, cause: Throwable = null) extends Exceptio
     sw.write(toString + "\n")
     sw.write("\t...\n")
     trimmed.foreach(ste => sw.write(s"\tat $ste\n"))
-    sw.write("\t... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)\n")
+    sw.write("\t... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)\n") // scalastyle:ignore line.size.limit
     sw.toString
   }
 }
@@ -80,6 +80,7 @@ private[chisel3] class ErrorLog {
 
   /** Throw an exception if any errors have yet occurred. */
   def checkpoint(): Unit = {
+    // scalastyle:off line.size.limit regex
     deprecations.foreach { case ((message, sourceLoc), count) =>
       println(s"${ErrorLog.depTag} $sourceLoc ($count calls): $message")
     }
@@ -112,6 +113,7 @@ private[chisel3] class ErrorLog {
       // No fatal errors, clear accumulated warnings since they've been reported
       errors.clear()
     }
+    // scalastyle:on line.size.limit regex
   }
 
   /** Returns the best guess at the first stack frame that belongs to user code.
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index c05d402d..0b0d1871 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -7,6 +7,8 @@ import core._
 import chisel3.internal._
 import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo}
 
+// scalastyle:off number.of.types
+
 case class PrimOp(val name: String) {
   override def toString: String = name
 }
@@ -77,7 +79,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   protected def minWidth: Int
   if (forcedWidth) {
     require(widthArg.get >= minWidth,
-      s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
+      s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") // scalastyle:ignore line.size.limit
   }
 }
 
@@ -261,6 +263,7 @@ abstract class Definition extends Command {
   def id: HasId
   def name: String = id.getRef.name
 }
+// scalastyle:off line.size.limit
 case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
 case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition