diff options
| author | Richard Lin | 2017-07-28 14:45:09 -0700 |
|---|---|---|
| committer | Adam Izraelevitz | 2017-07-28 14:45:09 -0700 |
| commit | 004938693112b2be268b0ee8d91874ba2d993ec3 (patch) | |
| tree | dcacd98e6a66648f45f4d8aa5a3d5e351fe512ca /chiselFrontend/src/main/scala/chisel3/internal | |
| parent | 2666b809a8964a3ec396714c36bd54469e943516 (diff) | |
Black box top-level IO fix (#655)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index cca368ef..6e18792c 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -274,6 +274,6 @@ abstract class Component extends Arg { def ports: Seq[Port] } case class DefModule(id: UserModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component -case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], params: Map[String, Param]) extends Component +case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: UserDirection, params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component], annotations: Seq[Annotation] = Seq.empty) |