Ensure names work for bundles and literals. (#853)

Fixes #852

2 files changed, 20 insertions, 3 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index 360994b1..ce4e1e88 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -112,11 +112,15 @@ private[chisel3] trait HasId extends InstanceId {
   private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
   private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
   private[chisel3] def getRef: Arg = _ref.get
+  private[chisel3] def getOptionRef: Option[Arg] = _ref
 
   // Implementation of public methods.
   def instanceName: String = _parent match {
     case Some(p) => p._component match {
-      case Some(c) => getRef fullName c
+      case Some(c) => _ref match {
+        case Some(arg) => arg fullName c
+        case None => suggested_name.getOrElse("??")
+      }
       case None => throwException("signalName/pathName should be called after circuit elaboration")
     }
     case None => throwException("this cannot happen")
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 6b555a82..b6630f7f 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -53,13 +53,26 @@ abstract class Arg {
 }
 
 case class Node(id: HasId) extends Arg {
-  override def fullName(ctx: Component): String = id.getRef.fullName(ctx)
-  def name: String = id.getRef.name
+  override def fullName(ctx: Component): String = id.getOptionRef match {
+    case Some(arg) => arg.fullName(ctx)
+    case None => id.suggestedName.getOrElse("??")
+  }
+  def name: String = id.getOptionRef match {
+    case Some(arg) => arg.name
+    case None => id.suggestedName.getOrElse("??")
+  }
 }
 
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   private[chisel3] def forcedWidth = widthArg.known
   private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+  override def fullName(ctx: Component): String = name
+  // Ensure the node representing this LitArg has a ref to it and a literal binding.
+  def bindLitArg[T <: Bits](bits: T): T = {
+    bits.bind(ElementLitBinding(this))
+    bits.setRef(this)
+    bits
+  }
 
   protected def minWidth: Int
   if (forcedWidth) {