diff options
4 files changed, 81 insertions, 11 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index 35f6c978..10b6ec8e 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -604,8 +604,7 @@ trait UIntFactory { val lit = ULit(value, width) val result = new UInt(lit.width) // Bind result to being an Literal - result.bind(ElementLitBinding(lit)) - result + lit.bindLitArg(result) } /** Create a UInt with the specified range */ @@ -757,8 +756,7 @@ trait SIntFactory { protected[chisel3] def Lit(value: BigInt, width: Width): SInt = { val lit = SLit(value, width) val result = new SInt(lit.width) - result.bind(ElementLitBinding(lit)) - result + lit.bindLitArg(result) } } @@ -828,8 +826,9 @@ trait BoolFactory { */ protected[chisel3] def Lit(x: Boolean): Bool = { val result = new Bool() - result.bind(ElementLitBinding(ULit(if (x) 1 else 0, Width(1)))) - result + val lit = ULit(if (x) 1 else 0, Width(1)) + // Ensure we have something capable of generating a name. + lit.bindLitArg(result) } } @@ -1086,8 +1085,8 @@ object FixedPoint { def apply(value: BigInt, width: Width, binaryPoint: BinaryPoint): FixedPoint = { val lit = FPLit(value, width, binaryPoint) val newLiteral = new FixedPoint(lit.width, lit.binaryPoint) - newLiteral.bind(ElementLitBinding(lit)) - newLiteral + // Ensure we have something capable of generating a name. + lit.bindLitArg(newLiteral) } /** diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index 360994b1..ce4e1e88 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -112,11 +112,15 @@ private[chisel3] trait HasId extends InstanceId { private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index))) private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref)) private[chisel3] def getRef: Arg = _ref.get + private[chisel3] def getOptionRef: Option[Arg] = _ref // Implementation of public methods. def instanceName: String = _parent match { case Some(p) => p._component match { - case Some(c) => getRef fullName c + case Some(c) => _ref match { + case Some(arg) => arg fullName c + case None => suggested_name.getOrElse("??") + } case None => throwException("signalName/pathName should be called after circuit elaboration") } case None => throwException("this cannot happen") diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 6b555a82..b6630f7f 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -53,13 +53,26 @@ abstract class Arg { } case class Node(id: HasId) extends Arg { - override def fullName(ctx: Component): String = id.getRef.fullName(ctx) - def name: String = id.getRef.name + override def fullName(ctx: Component): String = id.getOptionRef match { + case Some(arg) => arg.fullName(ctx) + case None => id.suggestedName.getOrElse("??") + } + def name: String = id.getOptionRef match { + case Some(arg) => arg.name + case None => id.suggestedName.getOrElse("??") + } } abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { private[chisel3] def forcedWidth = widthArg.known private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth) + override def fullName(ctx: Component): String = name + // Ensure the node representing this LitArg has a ref to it and a literal binding. + def bindLitArg[T <: Bits](bits: T): T = { + bits.bind(ElementLitBinding(this)) + bits.setRef(this) + bits + } protected def minWidth: Int if (forcedWidth) { diff --git a/src/test/scala/chiselTests/InstanceNameSpec.scala b/src/test/scala/chiselTests/InstanceNameSpec.scala new file mode 100644 index 00000000..30dc46ba --- /dev/null +++ b/src/test/scala/chiselTests/InstanceNameSpec.scala @@ -0,0 +1,54 @@ +// See LICENSE for license details. + +package chiselTests + +import chisel3._ +import chisel3.experimental.{DataMirror, FixedPoint} +import chisel3.testers.BasicTester + +class InstanceNameModule extends Module { + val io = IO(new Bundle { + val foo = Input(UInt(32.W)) + val bar = Output(UInt(32.W)) + }) + val x = 3.U + val y = UInt(8.W) + val z = new Bundle { + val foo = UInt(8.W) + } + + val q = Module(new util.Queue(UInt(32.W), 4)) + + io.bar := io.foo + x +} + +class InstanceNameSpec extends ChiselFlatSpec { + behavior of "instanceName" + val moduleName = "InstanceNameModule" + var m: InstanceNameModule = _ + elaborate { m = new InstanceNameModule; m } + + it should "work with module IO" in { + val io = m.io.pathName + assert(io == moduleName + ".io") + } + + it should "work with internal vals" in { + val x = m.x.pathName + val y = m.y.pathName + val z = m.z.pathName + assert(x == moduleName + ".UInt<2>(\"h03\")") + assert(y == moduleName + ".y") + assert(z == moduleName + ".z") + } + + it should "work with bundle elements" in { + val foo = m.z.foo.pathName + assert(foo == moduleName + ".z.foo") + } + + it should "work with modules" in { + val q = m.q.pathName + assert(q == moduleName + ".q") + } +} |