diff options
| author | Schuyler Eldridge | 2020-01-28 09:40:52 -0500 |
|---|---|---|
| committer | Schuyler Eldridge | 2020-02-06 10:36:44 -0500 |
| commit | 6a3eb3188c983268fab0f64ef4681b403cc2052d (patch) | |
| tree | 20c8c011718aaff7a2068108e4af23e60ad2838c /chiselFrontend/src/main/scala/chisel3/internal | |
| parent | b171f20d945487c79b18c18a2e8db98254f6e3e9 (diff) | |
Emit FIRRTL andr, orr for Bits.{andR, orR}
Change the emission strategy for Bits methods andR and orR to emit
FIRRTL bitwise reduce operations andr and orr.
Add two tests that assert the correct behavior of these operations in
BitwiseOpsSpec.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index a16d84bb..d98bebcd 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -47,6 +47,8 @@ object PrimOp { val NotEqualOp = PrimOp("neq") val NegOp = PrimOp("neg") val MultiplexOp = PrimOp("mux") + val AndReduceOp = PrimOp("andr") + val OrReduceOp = PrimOp("orr") val XorReduceOp = PrimOp("xorr") val ConvertOp = PrimOp("cvt") val AsUIntOp = PrimOp("asUInt") |