Emit FIRRTL andr, orr for Bits.{andR, orR}

Change the emission strategy for Bits methods andR and orR to emit
FIRRTL bitwise reduce operations andr and orr.

Add two tests that assert the correct behavior of these operations in
BitwiseOpsSpec.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

2 files changed, 4 insertions, 6 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/Bits.scala b/chiselFrontend/src/main/scala/chisel3/Bits.scala
index 57ce98d2..96eb74a4 100644
--- a/chiselFrontend/src/main/scala/chisel3/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Bits.scala
@@ -581,13 +581,9 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
   final def xorR(): Bool = macro SourceInfoTransform.noArg
 
   /** @group SourceInfoTransformMacro */
-  def do_orR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this =/= 0.U
+  def do_orR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, OrReduceOp)
   /** @group SourceInfoTransformMacro */
-  def do_andR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = width match {
-    // Generate a simpler expression if the width is known
-    case KnownWidth(w) => this === ((BigInt(1) << w) - 1).U
-    case UnknownWidth() =>  ~this === 0.U
-  }
+  def do_andR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, AndReduceOp)
   /** @group SourceInfoTransformMacro */
   def do_xorR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, XorReduceOp)
 
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index a16d84bb..d98bebcd 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -47,6 +47,8 @@ object PrimOp {
   val NotEqualOp = PrimOp("neq")
   val NegOp = PrimOp("neg")
   val MultiplexOp = PrimOp("mux")
+  val AndReduceOp = PrimOp("andr")
+  val OrReduceOp = PrimOp("orr")
   val XorReduceOp = PrimOp("xorr")
   val ConvertOp = PrimOp("cvt")
   val AsUIntOp = PrimOp("asUInt")