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2020-03-25Rename subprojects to more canonical namesJack Koenig
* Rename coreMacros to macros * Rename chiselFrontend to core Also make each subproject publish with "chisel3-" as a prefix
2020-03-23Remove toNamed (and friends) deprecation. (#1377)Jim Lawson
* Remove toNamed (and friends) deprecation. * Add inadvertently deleted leading double quote. * Remove commented out deprecations.
2020-03-23Add NoChiselNamePrefix to ignore instances in @chiselName (#1383)Jack Koenig
Add trait chisel3.experimental.NoChiselNamePrefix which causes @chiselName to skip naming of the instance effectively preventing it from prefixing any vals inside the instance. It can be applied to classes such that all instances of that class have this property, or to individual instances (via creating an anonymous class inline). Also add basic ScalaDoc for NoChiselNamePrefix and chiselName.
2020-03-21Use innermost builder cause to trim stack trace (#1380)Schuyler Eldridge
Change the logic for determining which nested ChiselException cause to use for a trimmed stack trace. Previously, this would use the outermost. This commit changes this to use the innermost. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-19Add Scaladoc to ChiselExceptionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-19Safer generation of ChiselException.builderNameSchuyler Eldridge
Change ChiselException.builderName to compute the name of Chisel's internal Builder as opposed to hard-coding this with a string. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-19Code style improvementSchuyler Eldridge
Co-authored-by: Jack Koenig <koenig@sifive.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-19Report trimmed stack trace of Builder causeSchuyler Eldridge
Changes the behavior of ChiselException stack trace trimming to use either the first exception that includes a method from the Builder or the outer exception. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-03-06Make implicit clock and reset final vals (#1360)Jack Koenig
Overriding will always result in a NullPointerException
2020-03-06Provide API to set concrete type of implicit reset (#1361)Jack Koenig
Introduces mutually-exclusive traits RequireAsyncReset and RequireSyncReset to set the type of the implicit reset in MultiIOModules. The Scala-type remains Reset, but the Chisel elaboration-time checks apply. Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-19Patch fix #1109 (#1346)Jack Koenig
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-12Fix := of Reset and AsyncReset to DontCare (#1336)Jack Koenig
2020-02-11Clone child elements lazily in Vec (#1329)Jack Koenig
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
2020-02-10Printf: Add support for tabs, and give helpful error messages (#1323) (#1326)Jack Koenig
Co-authored-by: Megan Wachs <megan@sifive.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-06Emit FIRRTL andr, orr for Bits.{andR, orR}Schuyler Eldridge
Change the emission strategy for Bits methods andR and orR to emit FIRRTL bitwise reduce operations andr and orr. Add two tests that assert the correct behavior of these operations in BitwiseOpsSpec. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-05Add information about widths to RegNext (#1318)Schuyler Eldridge
Adds additional Scaldoc to the RegNext object that (1) indicates that the width is not set and (2) shows an example of how to construct a RegNext-like construct with a set width. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
* Add support for readUnderWrite to SyncReadMem * Add write collision behavior test to MemorySpec * Update constant names
2020-01-31Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-25Fixed code example typo in comment (#1294)Leway Colin
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-25Remove redundancy code (#1296)Leway Colin
* Remove redundancy code * Remove blank line * BitPat supports whitespace and underscores, presumably for human readability. The BitPat.parse factory though did not remove these from the returned count. This fixes that adds whitespace and underscores to the unit tests This is an updated vesion of Chisel PR #1069 Co-authored-by: Chick Markley <chick@qrhino.com> Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-23Minor changes - update comments, use MaxBitsBigIntToBigDecimal instead of ↵Jim Lawson
'108'. (#1309) Co-authored-by: Chick Markley <chick@qrhino.com>
2020-01-22Update comment for Clock.asBool()Jim Lawson
2020-01-22Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-22Merge branch 'master' into big-decimal-methods-for-num-typesChick Markley
2020-01-22Change when/switch thunk type to Any (#1308)Schuyler Eldridge
* Change when thunks return type to Any Changes the type of the thunk for when and WhenContext methods from call-by-name Unit to call-by-name Any. This prevents a warning (-Ywarn-value-discard) where a when thunk is returning something other than Unit that is then discarded, e.g., another WhenContext. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> * Change switch thunk return to type to Any Changes the type of switch thunks from call-by-name Unit to call-by-name Any. This prevents a warning (-Ywarn-value-discard) when the internals of a switch block return something other than Unit which is then discarded. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-01-21Merge branch 'master' into big-decimal-methods-for-num-typeschick
# Conflicts: # src/test/scala/chiselTests/IntervalSpec.scala
2020-01-07Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-07Remove over design (#1237)Leway Colin
Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: Chick Markley <chick@qrhino.com>
2019-12-19Removed accidentally introduced parenschick
2019-12-18Add method asBool to Clock.chick
Shortcut for .asUInt.asBool Added test to show it works
2019-12-18- New trait HasBinaryPoint which provides literal values as double and big ↵chick
decimal - made .F and .I work for creating fixed point and interval lits from big decimal - Added NumObject trait which provides new math conversions - Made a Num object that extends NumObject - Add this trait to FixedPoint and Interval for backward compatibility - Removed code that is now in NumObject, keeping things DRY - Add tests to FixedPointSpec to show lit conversion to double and big decimal - Add tests to IntervalSpec to show lit conversion to double and big decimal - Add tests to LiteralExtractorSpec to show general math conversions between BigInts with binary points and double and big decimal
2019-12-17Merge branch 'master' into interval-fix-2Chick Markley
2019-12-17Band aid until litOption is implemented for Aggregates. (#1277)Jim Lawson
This is just a band aid until an Aggregate `isLit()` method (for which work has begun) is implemented.
2019-12-12Fixed problem creating Interval literals with full rangeschick
- boundary testing was not taking binary point into account correctly - add tests to show where things work and where they are supposed to fail
2019-12-11- Change getPossibleValues of Interval to return a NumericRange former Seq ↵chick
materialized all values - Fixed computation in getHighestPossibleValue, erroneously was using lower intead of upper
2019-12-04Add ChiselEnum to BundleLiterals (#1215)Zhuanhao Wu
2019-12-02Fix asTypeOf for Clock (#1258)Jack Koenig
2019-11-29Fix deprecation warning that leaks into user code (#1256)Jack Koenig
Data.isLit called Data.litArg which would trigger a Chisel runtime deprecation warning in user code with source locator Data.scala:488
2019-11-27Fix bidirectional Wire with Analog (#1252)Jack Koenig
2019-11-17Improve error message when assigning from Seq to Vec (#1239)Andrew Waterman
2019-11-15Enable @chiselName on non-module classes (#1209)John's Brew
2019-11-05Support literals cast to aggregates as async reset reg init values (#1225)Jack Koenig
Accomplished by changing the code gen for casting literals to aggregates. Rather than connecting the literal to a wire that is then bit selected from, just bit select from the literal which saves the creation of an intermediate wire and matches FIRRTL's semantics for legal async reset initial values.
2019-11-02Better anonymous and class-in-function desiredNameSchuyler Eldridge
This changes the desired name of a Module to provide non-numeric naming for anonymous Modules and Modules defined inside function bodies. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-18Interval Data Type Support for Chisel (#1210)Chick Markley
Plan to be released with 3.3. Breaks experimental Range API. Adds new Interval type and associated support. This commit adds the following: - Renamed Range to IntervalRange to avoid name collision with scala Range - Changed RangeTransform macro to Return an IntervalRange - Improved error messages on missing comma or decimal - Added notational support for binary point - Some formatting cleanup also - SIntFactory - Change to use IntervalRange API - UIntFactory - UInt from range has custom width computation - It does not need to deal with lowerbound extending bit requirements - Code to handle special case of range"[0,0]" to have a width of 1 - IR.scala - Removed Bound and other constraint code that was duplicating firrtl stuff - Added new RangeType - Added IntervalRange class and object - RangeSpec - modified just a bit to handle notational differences - previous range interpolator returned tuple now returns IntervalRange - Add IntervalType to emitter - Added IntervalSpec with many tests - Added ScalaIntervalSimulatorSpec which tests golden model for Interval - Added ScalaIntervalSimulator which is a golden model for Interval - This gold may not have been polished to a high sheen - Add IntervalLit cases to Converter - Add Interval PrimOps to IR - asInterval, wrap, squz, clip, setp, decp, incp - Add IntervalLit class to IR - Add Interval to MonoConnect - Add Interval Type to Bits (in experimental package) - add conversions to Interval from other types - Add Interval clone stuff to Data - Add Literal creation helpers to chisel3 package - these may move to experimental if I can figure that out
2019-10-08Fix direction of dynamic index in complex Vec (#1196)Jack Koenig
Dynamically indexing a Vec of Flipped bidirectional Bundles would get the wrong directions on the elements of the Bundles Fixes #1192
2019-10-07Improve desiredName for nested objects/classesSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-16Da steve101 tree reduce (#485)Jack Koenig
* Add a tree reduce function to Vec * Change function names of reduce operation function in Vec * Change reference to single layer operation in Vec.reduce * Commint name change for pair macro * Remove pair, call not necessary and can just be used from grouped(2) and map * Changed to reduceTree, added default identity function for single reduce. * Change style of Vec.reduceTree and tests to chisel3 and canonical Scala style * Cleanup Vec initialization, implicitCompileOptions
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
* Move dontTouch out of experimental package. * Move RawModule, MultiIOModule out of experimental. * Respond to comments - Move LagacyModule from experimental to internal. *NOTE*: At some point, these module definitions (especially those in separate packages) should be moved to individual files at the appropriate location in the source tree. The current organization is purely to support comparison with prior versions. * Fix up a few more imports.
2019-08-28refactor out _Factory traits + address EOF WSKamyar Mohajerani
2019-08-28Refactor Element, Num, and Analog classes to their own files (no functional ↵Kamyar Mohajerani
changes)
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