Fixed code example typo in comment (#1294)

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

2 files changed, 5 insertions, 5 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
index 8141fdba..84e959a5 100644
--- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
@@ -121,7 +121,7 @@ trait VecFactory extends SourceInfoDoc {
   *  {{{
   *    val io = IO(new Bundle {
   *      val in = Input(Vec(20, UInt(16.W)))
-  *      val addr = UInt(5.W)
+  *      val addr = Input(UInt(5.W))
   *      val out = Output(UInt(16.W))
   *    })
   *    io.out := io.in(io.addr)
@@ -696,8 +696,8 @@ package experimental {
   *        val outPacket = Output(new Packet)
   *      })
   *      val reg = Reg(new Packet)
-  *      reg <> inPacket
-  *      outPacket <> reg
+  *      reg <> io.inPacket
+  *      io.outPacket <> reg
   *   }
   * }}}
   */
diff --git a/chiselFrontend/src/main/scala/chisel3/Reg.scala b/chiselFrontend/src/main/scala/chisel3/Reg.scala
index 51c59bdb..a3e6b2a0 100644
--- a/chiselFrontend/src/main/scala/chisel3/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Reg.scala
@@ -108,13 +108,13 @@ object RegNext {
   * val x = Wire(UInt())
   * val y = Wire(UInt(8.W))
   * val r1 = RegInit(x) // width will be inferred
-  * val r2 = RegInit(y) // width will be inferred
+  * val r2 = RegInit(y) // width is set to 8
   * }}}
   *
   * 3. [[Aggregate]] initializer - width will be set to match the aggregate
   *
   * {{{
-  * class MyBundle {
+  * class MyBundle extends Bundle {
   *   val unknown = UInt()
   *   val known   = UInt(8.W)
   * }