diff options
| author | Jack Koenig | 2019-11-27 16:29:32 -0800 |
|---|---|---|
| committer | GitHub | 2019-11-27 16:29:32 -0800 |
| commit | 2c53527f6c232121a2340e75c0109c1618fc2428 (patch) | |
| tree | fa453dd84cdd4dee2472414fd66f25d8c72c4757 /chiselFrontend | |
| parent | fdc41387d37abb8d2a75efa30a2d30d9373dd785 (diff) | |
Fix bidirectional Wire with Analog (#1252)
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala b/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala index 2a4aa5f5..37eb578d 100644 --- a/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala +++ b/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala @@ -57,10 +57,8 @@ final class Analog private (private[chisel3] val width: Width) extends Element { case SampleElementBinding(parent) => parent.topBinding } - // Analog counts as different directions based on binding context targetTopBinding match { - case WireBinding(_) => direction = ActualDirection.Unspecified // internal wire - case PortBinding(_) => direction = ActualDirection.Bidirectional(ActualDirection.Default) + case _: WireBinding | _: PortBinding => direction = ActualDirection.Bidirectional(ActualDirection.Default) case x => throwException(s"Analog can only be Ports and Wires, not '$x'") } binding = target |