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authorJack Koenig2019-11-27 16:29:32 -0800
committerGitHub2019-11-27 16:29:32 -0800
commit2c53527f6c232121a2340e75c0109c1618fc2428 (patch)
treefa453dd84cdd4dee2472414fd66f25d8c72c4757
parentfdc41387d37abb8d2a75efa30a2d30d9373dd785 (diff)
Fix bidirectional Wire with Analog (#1252)
-rw-r--r--chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala4
-rw-r--r--src/test/scala/chiselTests/AnalogSpec.scala21
2 files changed, 22 insertions, 3 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala b/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala
index 2a4aa5f5..37eb578d 100644
--- a/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala
+++ b/chiselFrontend/src/main/scala/chisel3/experimental/Analog.scala
@@ -57,10 +57,8 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
case SampleElementBinding(parent) => parent.topBinding
}
- // Analog counts as different directions based on binding context
targetTopBinding match {
- case WireBinding(_) => direction = ActualDirection.Unspecified // internal wire
- case PortBinding(_) => direction = ActualDirection.Bidirectional(ActualDirection.Default)
+ case _: WireBinding | _: PortBinding => direction = ActualDirection.Bidirectional(ActualDirection.Default)
case x => throwException(s"Analog can only be Ports and Wires, not '$x'")
}
binding = target
diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala
index d81ed009..c443ce7b 100644
--- a/src/test/scala/chiselTests/AnalogSpec.scala
+++ b/src/test/scala/chiselTests/AnalogSpec.scala
@@ -194,6 +194,27 @@ class AnalogSpec extends ChiselFlatSpec {
})
}
+ it should "work in bidirectional Aggregate wires" in {
+ class MyBundle extends Bundle {
+ val x = Input(UInt(8.W))
+ val y = Analog(8.W)
+ }
+ elaborate(new Module {
+ val io = IO(new Bundle {
+ val a = new MyBundle
+ })
+ val w = Wire(new MyBundle)
+ w <> io.a
+ })
+ elaborate(new Module {
+ val io = IO(new Bundle {
+ val a = Vec(1, new MyBundle)
+ })
+ val w = Wire(Vec(1, new MyBundle))
+ w <> io.a
+ })
+ }
+
it should "work with 3 blackboxes attached" in {
assertTesterPasses(new AnalogTester {
val mods = Seq.fill(2)(Module(new AnalogReaderBlackBox))