diff options
| author | Jack Koenig | 2016-12-21 14:33:07 -0800 |
|---|---|---|
| committer | Jack Koenig | 2017-02-08 18:00:32 -0800 |
| commit | 66a72ff64c46d8a9fdade77223de62b4dcfe2825 (patch) | |
| tree | 8ff97057072ed7ec1e1c64b3f1db774e2c09f99e /chiselFrontend/src/main/scala/chisel3/internal | |
| parent | 132b80edee2fb8e730d3b6f5eb5f36051a819525 (diff) | |
Add Analog type
Used for stitching Verilog inout through Chisel Modules (from BlackBox
to BlackBox)
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/internal')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 50400034..bee72817 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -263,6 +263,7 @@ case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command case class WhenEnd(sourceInfo: SourceInfo) extends Command case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command +case class Attach(sourceInfo: SourceInfo, locs: Seq[Node]) extends Command case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command case class Port(id: Data, dir: Direction) |